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CSR Bit Fields

RISC-V hpmcounter28 CSR Register

Address 0xC1CPrivilege UserAccess RO / XLENUser counters and performance-monitoring CSRs

hpmcounter28 is a Zihpm user-level read-only hardware performance counter for implementation-defined event counts. Zihpm depends on Zicsr.

Related Search Terms
hpmcounter28 CSRhpmcounter28 0xC1CHPM counter 28hardware performance counter 28mcounteren HPM28mhpmevent28
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand hpmcounter28 By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

Read-only shadow of mhpmcounter28. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

VALUE (bits XLEN-1:0) — Read-only shadow of mhpmcounter28. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

What This Field Controls

  • - Read-only shadow of mhpmcounter28. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hpmcounter28 is a RO CSR in user counters and performance-monitoring csrs at 0xC1C. Check privilege and implemented extensions before interpreting its bit fields.

hpmcounter28 address, lowest access privilege, and access class are checked against the official CSR table: 0xC1C, User, RO.
hpmcounter28 is a read-only shadow of mhpmcounter28; U-mode access requires both mcounteren.HPM28 and scounteren.HPM28 to permit it.
The implementation-defined mhpmevent28 selects the incrementing event; a legal implementation may make both this counter and its selector read-only zero.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - Confirm that the current hart implements hpmcounter28; accessing an unimplemented counter may raise an illegal-instruction exception or return a constant value.
  • - Use address 0xC1C and the lowest access privilege (User) to decide whether software may read it directly.
  • - U-mode reads require both mcounteren.HPM28 and scounteren.HPM28 to permit access. With V=1, hcounteren.HPM28=0 and mcounteren.HPM28=1 cause a virtual-instruction exception in VS-mode; VU-mode additionally requires scounteren.HPM28=1.

Risk Checks Before Writing

  • - hpmcounter28 is a read-only CSR; writes raise an illegal-instruction exception.

Put It Back Into A Real Flow

1

Read hpmcounter28 to obtain hardware or runtime state.

2

Interpret the returned value according to the field descriptions and do not attempt to write it back.

3

If reading fails at the current privilege level, handle the illegal-instruction exception path.

FAQ

Can hpmcounter28 be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records hpmcounter28 as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using hpmcounter28?

hpmcounter28 is a read-only shadow CSR. Check both HPM28 counter-enable bits; the platform defines the event selected by mhpmevent28.