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CSR Bit Fields

RISC-V hpmcounter31 CSR Register

Address 0xC1FPrivilege UserAccess RO / XLENUser counters and performance-monitoring CSRs

hpmcounter31 is a Zihpm user-level read-only hardware performance counter for implementation-defined event counts. Zihpm depends on Zicsr.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand hpmcounter31 By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

Read-only shadow of mhpmcounter31. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

VALUE (bits XLEN-1:0) — Read-only shadow of mhpmcounter31. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

What This Field Controls

  • - Read-only shadow of mhpmcounter31. Machine HPM counters support up to 64 bits; this CSR returns the low XLEN bits on RV32/RV64.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

  • - Confirm that the current hart implements hpmcounter31; accessing an unimplemented counter may raise an illegal-instruction exception or return a constant value.
  • - Use address 0xC1F and the lowest access privilege (User) to decide whether software may read it directly.
  • - U-mode reads require both mcounteren.HPM31 and scounteren.HPM31 to permit access. With V=1, hcounteren.HPM31=0 and mcounteren.HPM31=1 cause a virtual-instruction exception in VS-mode; VU-mode additionally requires scounteren.HPM31=1.

Risk Checks Before Writing

  • - hpmcounter31 is a read-only CSR; writes raise an illegal-instruction exception.

Put It Back Into A Real Flow

1

Read hpmcounter31 to obtain hardware or runtime state.

2

Interpret the returned value according to the field descriptions and do not attempt to write it back.

3

If reading fails at the current privilege level, handle the illegal-instruction exception path.