RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V hpmcounter3h CSR Register

Address 0xC83Privilege UserAccess RO / RV32 high-half / 32-bitUser counters and performance-monitoring CSRs

hpmcounter3h is the Zihpm RV32 user-level read-only high-half CSR for hpmcounter3 bits 63:32. Zihpm depends on Zicsr.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand hpmcounter3h By Bit Fields

0 key fields

What To Check First When Reading This CSR

  • - Confirm that the current hart implements hpmcounter3; accessing an unimplemented counter may raise an illegal-instruction exception or return a constant value.
  • - Use address 0xC83 and the lowest access privilege (User) to decide whether software may read it directly.
  • - U-mode reads require both mcounteren.HPM3 and scounteren.HPM3 to permit access. With V=1 and XLEN=32, hcounteren.HPM3=0 and mcounteren.HPM3=1 cause a virtual-instruction exception in VS-mode; VU-mode additionally requires scounteren.HPM3=1. On RV64, any access to this high-half CSR always raises an illegal-instruction exception.

Risk Checks Before Writing

  • - hpmcounter3h is a read-only CSR; writes raise an illegal-instruction exception.

Put It Back Into A Real Flow

1

Read hpmcounter3h to obtain hardware or runtime state.

2

Interpret the returned value according to the field descriptions and do not attempt to write it back.

3

If reading fails at the current privilege level, handle the illegal-instruction exception path.