RISC-V hvienh CSR Register

Address 0x618Privilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

hvienh is a upper 32 bits of hvien.

Related Search Terms

hvienh CSR hvienh 0x618 RISC-V AIA hvien upper half virtual interrupt

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32HVIEN_HIGH31:0RW

Field Map

Understand hvienh By Bit Fields

1 key fields

31:0

HVIEN_HIGH

hvienh is the RV32 access window for hvien[63:32]. The 0/1 meanings apply only to official AIA-defined upper-half hvien bits that are implemented as writable and valid; reserved, undefined, unimplemented, or non-writable bits do not gain fixed injection semantics.

HVIEN_HIGH (bits 31:0) — hvienh is the RV32 access window for hvien[63:32]. The 0/1 meanings apply only to official AIA-defined upper-half hvien bits that are implemented as writable and valid; reserved, undefined, unimplemented, or non-writable bits do not gain fixed injection semantics.

What This Field Controls

- hvienh is the RV32 access window for hvien[63:32]. The 0/1 meanings apply only to official AIA-defined upper-half hvien bits that are implemented as writable and valid; reserved, undefined, unimplemented, or non-writable bits do not gain fixed injection semantics.

Common Values

0Disabled

For an official AIA-defined upper-half hvien bit that is implemented as writable and valid, the corresponding virtual interrupt injection is disabled; this meaning does not apply to reserved, undefined, unimplemented, or non-writable bits.

1Enabled

For an official AIA-defined upper-half hvien bit that is implemented as writable and valid, the corresponding virtual interrupt injection is enabled; delivery also depends on hvictl/hvip and target VS interrupt state. Reserved, undefined, unimplemented, or non-writable bits do not have this fixed 1 meaning.

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Official Basis & Search Notes

hvienh is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hvienh address, access class, and width are checked against the official CSR tables: 0x618, HRW, 32-bit RV32 high half.

AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.

Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Advanced Interrupt Architecture CSR chapter RISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

- hvienh is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hvienh, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hvienh be accessed through a supervisor CSR alias?

Do not treat hvienh as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hvienh?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.