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CSR Bit Fields

RISC-V hvienh CSR Register

Address 0x618Privilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

hvienh is the RV32 32-bit high-half access window for AIA hvien[63:32]; it does not exist on RV64.

Related Search Terms
hvienh CSRhvienh 0x618RV32 hvien high halfAIA virtual interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand hvienh By Bit Fields

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Official Basis & Search Notes

hvienh is the RV32 32-bit high-half access window for AIA hvien[63:32]; it does not exist on RV64.

AIA uses hvien for VS-level virtual-interrupt enables; bits 32:63 in this high half correspond to interrupt numbers 32-63, and an implementation may make a particular bit writable, read-only zero, or read-only one.
RISC-V Advanced Interrupt ArchitectureRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - This separate high-half CSR exists only when the defining extension is implemented and XLEN=32; it does not exist on RV64.
  • - AIA Table 5 and its RV32 high-half table define its address and HRW class; field writability and read-only-zero/read-only-one choices are implementation-defined.

Risk Checks Before Writing

  • - Write only fields that are explicitly implemented and writable; do not assign portable software meaning to reserved or specification-required read-only-zero bits.

Put It Back Into A Real Flow

1

Confirm that H and the optional extension defining the field are implemented, then access it from an M or HS context.

2

On RV32, use this address for bits 63:32 of the corresponding 64-bit CSR; do not access this address on RV64.