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CSR Bit Fields

RISC-V sideleg CSR Register

Address 0x103Privilege SupervisorAccess RW / XLENLegacy or draft-compatibility CSRs

Supervisor interrupt delegation register, delegates M-mode interrupts to S-mode. (Legacy/draft compatibility entry; not used as a standard Machine CSR in the current base privileged CSR table.)

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:12Interrupts11:0RW
Field Map

Understand sideleg By Bit Fields

1 key fields
11:0

Interrupts

RW

Delegate corresponding interrupt to S-mode

Interrupts (bits 11:0) — Delegate corresponding interrupt to S-mode.

What This Field Controls

  • - Delegate corresponding interrupt to S-mode

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements sideleg; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x103 and the lowest access privilege (Supervisor) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads sideleg to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.