RISC-V sireg4 CSR Register

Address 0x155Privilege SupervisorAccess RW / XLENSupervisor AIA, timer, and indirect interrupt CSRs

sireg4 (0x155) is an Sscsrind Supervisor indirect-register alias 4 that accesses extension state selected by siselect.

Related Search Terms

sireg4 CSR sireg4 0x155 sireg alias siselect CSR Sscsrind indirect CSR

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

ALIAS_DATA63:0Depends on select

Field Map

Understand sireg4 By Bit Fields

1 key fields

XLEN-1:0

ALIAS_DATA

Depends on select

Alias data window; exact read/write semantics are defined by the extension selected by siselect, and cannot be inferred from this CSR name for unimplemented select values.

ALIAS_DATA (bits XLEN-1:0) — Alias data window; exact read/write semantics are defined by the extension selected by siselect, and cannot be inferred from this CSR name for unimplemented select values.

What This Field Controls

- Alias data window; exact read/write semantics are defined by the extension selected by siselect, and cannot be inferred from this CSR name for unimplemented select values.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

sireg4 is not an independent fixed-meaning register; it is an alias window selected by siselect.

Sscsrind defines sireg* behavior through the siselect/sireg* combination and the selected extension.

Delegated-counter ranges may use sireg4 for high-half counter state on RV32, and accessing sireg4 when XLEN=64 raises an illegal-instruction exception; for CTR siselect 0x200..0x2FF, sireg4 is 0; AIA IMSIC interrupt-file state at 0x70..0xFF is accessed through sireg, and sireg2..6 raise illegal-instruction exceptions in those AIA ranges.

Do not assume zero reads, writability, or fixed side effects for unimplemented select values.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Smcsrind/Sscsrind RISC-V Advanced Interrupt Architecture - IMSIC CSRs RISC-V Privileged Architecture Manual - Smctr RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

- First confirm that the hart implements the extension containing sireg4; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
- Use address 0x155, the lowest access privilege, and the official access class to decide whether software may access it directly.
- Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

- When writing sireg4, modify only the officially defined target fields and preserve unchanged bits.
- Handle WARL, WLRL, WPRI, and reserved fields according to the official specification; do not overwrite the whole CSR as an ordinary integer.

Put It Back Into A Real Flow

First write siselect to choose the indirect-register number.

Then access the corresponding alias window through sireg4.

If the selected extension or window is not implemented, handle illegal-instruction exceptions or the officially specified UNSPECIFIED behavior.

For delegated-counter range 0x40..0x5F, accessing sireg4 when XLEN=64 raises an illegal-instruction exception; for AIA select ranges 0x30..0x3F or 0x70..0xFF, accessing sireg4 also raises an illegal-instruction exception; for CTR 0x200..0x2FF it is 0.

FAQ

Why are sireg4 bit fields unlike ordinary CSRs?

Because it is an alias window; bit fields depend on the current siselect value and selected extension.