RISC-V ssp CSR Register

Address 0x011Privilege User (access controlled by xenvcfg.SSE)Access URW (conditional access) / XLENUser-level Zicfiss CSR

ssp (0x011) is the Zicfiss unprivileged read-write CSR holding the XLEN-bit shadow stack pointer for the current privilege mode.

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Field Map

Understand ssp By Bit Fields

3 key fields

XLEN-1:3

High-order shadow stack pointer bits.

SSP (bits XLEN-1:3) — High-order shadow stack pointer bits.

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Conditionally RW

A pointer bit when UXLEN or SXLEN may be 32; otherwise read-only zero.

SSP[2] (bit 2) — A pointer bit when UXLEN or SXLEN may be 32; otherwise read-only zero.

This field is better understood together with surrounding context than as a fixed memorized enumeration.

1:0

RO zero

Always reads as zero.

Reserved (bits 1:0) — Always reads as zero.

This field is better understood together with surrounding context than as a fixed memorized enumeration.

- Below M-mode, menvcfg.SSE=0 causes an illegal-instruction exception; U-mode also requires senvcfg.SSE=1.
- VS/VU access can cause a virtual-instruction exception depending on henvcfg.SSE and senvcfg.SSE.

The operating system sets up a shadow stack for a Zicfiss-enabled process.

Use shadow-stack instructions only in a privilege mode where access is allowed.