RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V ustatus CSR Register

Address 0x000Privilege UserAccess RW / XLENLegacy or draft-compatibility CSRs

User-mode status register containing interrupt enable and privilege info. (Compatibility entry for legacy or non-current ratified base privileged specifications; confirm the source extension before use.)

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:5UPIE4RWReserved3:1UIE0RW
Field Map

Understand ustatus By Bit Fields

2 key fields
0

UIE

RW

User interrupt enable (shadow of sstatus.UIE)

UIE (bit 0) — User interrupt enable (shadow of sstatus.UIE).

What This Field Controls

  • - User interrupt enable (shadow of sstatus.UIE)

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4

UPIE

RW

User prior interrupt enable

UPIE (bit 4) — User prior interrupt enable.

What This Field Controls

  • - User prior interrupt enable

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

  • - Shadow copy of User-related bits of sstatus

Risk Checks Before Writing

  • - Writes may affect interrupt response

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads ustatus to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.