1:0
MODE
RWVector mode
MODE (bits 1:0) — Vector mode.
What This Field Controls
- - Vector mode
Common Values
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualCSR Bit Fields
RISC-V utvec CSR Register
Address 0x005Privilege UserAccess RW / XLENLegacy or draft-compatibility CSRs
User-mode trap vector base address. (Compatibility entry for legacy or non-current ratified base privileged specifications; confirm the source extension before use.)
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand utvec By Bit Fields
2 key fields
XLEN-1:2
BASE
RWTrap handler base
BASE (bits XLEN-1:2) — Trap handler base.
What This Field Controls
- - Trap handler base
Common Values
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualWhat To Check First When Reading This CSR
- - First confirm that the current hart implements utvec; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- - Use address 0x005 and the lowest access privilege (User) to decide whether software may read it directly.
- - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.
Risk Checks Before Writing
- - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.
Put It Back Into A Real Flow
1
During initialization or the relevant privileged flow, software reads utvec to observe the current state.
2
Modify only the target fields while preserving all other bits.
3
Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.