Does AMOMAXU.B return the post-operation value?
No. Like A-extension AMOs, rd receives the old value loaded from memory.
AMOMAXU.B
RISC-V AMOMAXU.B Instruction Details
Instruction ManualR-typeAtomic byte unsigned max: rd = *rs1 (sign-ext), *rs1 = umax(*rs1, rs2[7:0])
Instruction Syntax
amomaxu.b rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZabhaAtomic
Instruction Behavior
AMOMAXU.B (Zabha extension) atomically loads a byte from the address in rs1 into rd (sign-extended), compares it as an unsigned byte with the low byte of rs2, and stores the selected unsigned max value back. Supports aq/rl bits.
AMOMAXU.B Atomic Decode And Execute Animation
Shows Zabha byte atomic field decode, aq/rl ordering bits, memory read, and RMW state update.
rd
rs2
rs1
amomaxu.b,,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
11100
funct5
0
aq
0
rl
01011
rs2
01010
rs1
000
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0xE0B502AF
opcode
0101111 -> AMO
funct3
000 -> byte width
funct5
11100 -> AMOMAXU.B
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)=0x01 / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old byte 0x80
RMW
128 >= 1 -> 0x80
rd / memory
t0(x5) = 0xFFFFFF80; mem[0x00001000] = 0x80
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
Zabha-extension byte atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0xE0B502AF
syntax : amomaxu.b t0(x5), a1(x11), (a0(x10))
result : t0(x5) = 0xFFFFFF80; mem[0x00001000] = 0x80
Unsigned 8-bit Byte Comparison
old byte
0x80 (128)
rs2 byte
0x01 (1)
comparison
old >= rs2 -> old value
memory result
0x80
AMOMAXU.B selects the memory writeback byte using a unsigned 8-bit comparison; this is not a per-bit logical operation.
This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.
Quick Understanding & Search Notes
AMOMAXU.B is a Zabha 8-bit unsigned max instruction. It atomically reads the old memory value, selects the memory writeback with an unsigned 8-bit comparison, and writes the sign-extended old value to rd.
Only the 8-bit subword is operated on; upper bits of rs2 are ignored.
rd receives the old memory value sign-extended to XLEN; unsigned affects the min/max comparison, not rd extension.
The address must be naturally aligned to the operand size; aq/rl bits can provide release-consistency ordering semantics.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «amomaxu.b a0, a2, (a1)».
Network & Byte Order
Understand this scenario with real code like «amomaxu.b a0, a2, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rd returns the old memory value (sign-extended to XLEN), not the operation result
Unsigned maximum comparison; negative values become very large when interpreted as unsigned
Atomicity depends on natural alignment and implementation support
FAQ
Can AMOMAXU.B affect neighboring bytes?
Architecturally it modifies only the byte operand; Zabha provides native byte-granule atomic read-modify-write operations.