CTZW

RISC-V CTZW Instruction Details

Instruction ManualR-type

Count trailing zero bits in word (RV64)

Instruction Syntax

ctzw rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbBit Manipulation

Instruction Behavior

ctzw on RV64 examines only the low 32 bits of rs1 and returns a count from 0 to 32.

Quick Understanding & Search Notes

ctzw on RV64 examines only the low 32 bits of rs1 and returns a count from 0 to 32.

These instructions are part of a B-extension subset and operate on XLEN-wide integer register values.
If the low 32 bits are zero, the result is 32.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «ctzw x10, x11 ; x10 = trailing zeros in x11[31:0]».

Bit Operations & Masks

Understand this scenario with real code like «ctzw x10, x11 ; x10 = trailing zeros in x11[31:0]».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

If the low 32 bits are zero, the result is 32.

FAQ

Does ctzw access memory?

No. It reads integer register operands and writes rd only.

Does ctzw interpret signed numbers?

These bit operations work on bit patterns directly; aside from the specified word-width selection, arithmetic signed magnitude is not used.