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FLEQ.Q

RISC-V FLEQ.Q Instruction Details

Instruction ManualR-type

Quad-precision floating-point quiet less-or-equal comparison; writes x[rd]=1 when true, otherwise 0.

Instruction Syntax

fleq.q rd, rs1, rs2
Operand Breakdown
rd: destination integer register receiving a 0 or 1 comparison result.
rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
ZfaQFloating-Point Compare
Related Search Terms
FLEQ.Q instructionRISC-V FLEQ.Qfleq.q syntaxfleq.q NaNfleq.q NV flagquad-precision floating compare

Instruction Behavior

FLEQ.Q compares the quad-precision floating-point values in f[rs1] and f[rs2] and writes the Boolean result to integer register rd. It is a quiet comparison: quiet NaNs do not set NV, signaling NaNs set NV, and any NaN operand makes the result 0. It requires Zfa and Q; Q depends on D and extends FLEN to 128. Its OP-FP encoding has funct5=10100, fmt=11, and funct3=100 in bits [14:12] (bit 14 set) to select FLEQ, not an rm rounding mode.

FLEQ.Q Decode And Execute Animation

Shows the Zfa + Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FLEQ semantics, then write rd.

rd
rs1
rs2
fleq.q
,
,
Execution Context
FLEN=128 / fmt=Q (11)
funct3: quiet less-or-equal compare
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10100
FLEQ
11
fmt=Q
01100
rs2
01011
rs1
100
funct3=100
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xA6C5C553
opcode
1010011 -> OP-FP
funct5/fmt
10100 + Q(11) -> FLEQ.Q
funct3
100 -> quiet less-or-equal compare
rd/rs
a0(x10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.

encoding: 0xA6C5C553
syntax : fleq.q a0(x10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Quad-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.25
result
Awaiting Execute

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.

This animation shows only Zfa + Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FLEQ.Q writes the floating-point comparison result to integer register x[rd]. It has quiet-comparison semantics, useful when quiet NaNs should not raise NV.

It writes 1 when rs1 <= rs2 is true, otherwise 0; any NaN operand writes 0 and only a signaling NaN sets NV.
FLEQ.Q requires Zfa and Q; Q depends on D and F and extends FLEN to 128.
Its OP-FP encoding uses funct5=10100, fmt=11, and funct3=100 in bits [14:12] (bit 14 set) to select FLEQ; rd is an integer register and funct3 is not an rm rounding field.
Applies to RV32/RV64 Zfa + Q (Q depends on D, and D on F); FLEN=128. Required extensions and FP state must be enabled; sources narrower than FLEN require valid NaN-boxing, otherwise they are read as canonical qNaN.
With rd=x0, the integer result is discarded and x0 stays 0; NV still accrues in fflags. A quiet comparison that does not set NV for qNaN does not clear an existing NV.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, §26.6

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «fleq.q x10, f0, f1 # f0=1.5, f1=2.25 -> x10=1; initial fflags=0, final fflags=0».

Floating-Point Conditions

Understand this scenario with real code like «fleq.q x10, f0, f1 # f0=1.5, f1=2.25 -> x10=1; initial fflags=0, final fflags=0».

Pre-Use Checklist

Syntax Check
  • rd: destination integer register receiving a 0 or 1 comparison result.
  • rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
Semantic Check
  • Confirm the result is written to an integer register and is only 0 or 1.
  • Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.

Pitfalls / Common Confusions

Quiet comparisons set NV only for signaling NaNs; a quiet NaN only makes the result 0.
rd is an integer register and receives 0 or 1, not a floating-point value.
The comparison does not use the rm rounding mode.

FAQ

Is rd a floating-point register for FLEQ.Q?

No. rd is an integer register holding the Boolean result 0 or 1.

What happens on NaN operands?

Any NaN operand makes the result 0; only signaling NaNs set NV.