How is FMSUB.S different from FMUL plus add/subtract?
FMSUB.S is fused: the product is not first rounded into an intermediate FP result; the whole expression is rounded once at the end according to rm.
FMSUB.S
RISC-V FMSUB.S Instruction Details
Instruction ManualR4-typesingle-precision fused multiply-subtract: rd = (rs1 * rs2) - rs3, with one final rounding according to rm.
Instruction Syntax
fmsub.s rd, rs1, rs2, rs3, rm
Operand Breakdown
rd: destination floating-point register.
rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
rm: rounding-mode field for the final fused multiply-add/subtract result.
FFloating-Point Arithmetic
Instruction Behavior
FMSUB.S uses the R4 four-register format for single-precision fused multiply-subtract. The rs1*rs2 product is not rounded or written as an intermediate result; it is combined with rs3 as one fused expression, rounded once according to rm, and written to rd.
FMSUB.S Decode And Execute Animation
Shows the F-extension single-precision R4 fused multiply operation flow: decode fields, read FP operands, perform FMSUB semantics, then write rd.
rd
rs1
rs2
rs3
rm
fmsub.s
,
,
,
,
Execution Context
FLEN=>=32 / fmt=S (00)
rounding: RNE nearest-even
fflags: invalid input, using default example
These execution-context inputs are invalid and are not used for encoding or execution: fa1(f11) value (1.5), fa2(f12) value (2), fa3(f13) value (0.5). The animation is using legal FMSUB.S default example values.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01101
rs3
00
fmt=S
01100
rs2
01011
rs1
000
rm
01010
rd
1000111
MSUB
Execution Data Path
instruction
0x68C58547
opcode
1000111 -> MSUB
rs3/fmt
fa3(f13) + S(00) -> R4 FMSUB
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12) / fa3(f13)
read
1.5, 2.0, 0.5
fused op
(1.5 * 2.0) - 0.5 = 2.5
write
fa0(f10) = 2.5; invalid input, using default example
Current Step
Fetch: show the 32-bit R4 encoding
The word is split as an R4-type instruction; FMSUB.S uses its dedicated major opcode 1000111, not the ordinary OP-FP opcode.
encoding: 0x68C58547
syntax : fmsub.s fa0(f10), fa1(f11), fa2(f12), fa3(f13), rne
result : fa0(f10) = 2.5; invalid input, using default example
This animation accepts only whitelisted finite exact examples, and the computed result must also stay in the whitelist; NaN, infinity, and rounding-boundary paths are covered in static text. Invalid input is not used for calculation.
Single-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
rs3
fa3(f13) = 0.5
result
(1.5 * 2.0) - 0.5 = 2.5
This animation accepts only whitelisted finite exact examples, and the computed result must also stay in the whitelist; NaN, infinity, and rounding-boundary paths are covered in static text. Invalid input is not used for calculation.
This animation shows only F-extension ISA-visible R4 encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMSUB.S's key points are R4 encoding and fused semantics: rs3 is a real third source register, and the product plus/minus term forms one exact intermediate expression that is rounded only once.
R4 major opcode=1000111 identifies the MSUB fused operation class, and fmt=S selects the single-precision format.
The encoded field order is rs3 | fmt | rs2 | rs1 | rm | rd | opcode; this differs from ordinary OP-FP R-type instructions.
The semantic expression is rd = (rs1 * rs2) - rs3, and the fused operation is rounded once at the end according to rm/frm.
The F extension defines the 32-bit S format; the animation accepts only finite, exactly checkable whitelisted examples, while NaN, infinity, overflow, underflow, and inexact paths are covered in this page's static explanation.
Common Usage Scenarios
Fused Floating Point
Understand this scenario with real code like «fmsub.s f0, f1, f2, f3, rne # f0 = (rs1 * rs2) - rs3».
Numerical Computing
Understand this scenario with real code like «fmsub.s f0, f1, f2, f3, rne # f0 = (rs1 * rs2) - rs3».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
- rm: rounding-mode field for the final fused multiply-add/subtract result.
Semantic Check
- Confirm rs3 participates in the fused operation and the result is rounded only once at the end.
- Confirm the sign rules for FNMADD/FNMSUB match the intended operation.
Pitfalls / Common Confusions
FMSUB.S is a fused operation, not the same as FMUL followed by FADD/FSUB with two roundings.
In the R4 encoding, bits 31..27 are the rs3 field; do not decode them as an ordinary OP-FP R-type funct5 field.
rm controls the single final rounding; rm=101 and 110 are reserved, while rm=111 selects frm and frm=101 through 111 gives reserved behavior.
If one multiplicand is infinity and the other is zero, NV must be set even when rs3 is a quiet NaN; other applicable OF, UF, and NX conditions also accrue in fflags.
The FNMSUB/FNMADD sign rules are easy to confuse: FNMSUB is -(rs1*rs2)+rs3, while FNMADD is -(rs1*rs2)-rs3.
FAQ
Why is FMSUB.S R4-type?
It needs rd, rs1, rs2, rs3, and rm fields; bits 31..27 hold rs3, not an ordinary R-type funct5 field.
Can FMSUB.S set fflags?
It can set FP exception flags under the official FP rules, such as inexact, overflow, underflow, or invalid operation; the default animation uses exact finite values, so it shows fflags remaining 0.