Does MIN return 0 or 1?
No. It returns the original XLEN-bit value selected from rs1 or rs2 by the comparison rule.
MIN
RISC-V MIN Instruction Details
Instruction ManualR-typeReturn the minimum of rs1 and rs2 using signed comparison.
Instruction Syntax
min rd, rs1, rs2
Operand Breakdown
rd: x0–x31; receives the selected operand's original XLEN-bit pattern; writes to x0 are discarded.
rs1, rs2: compared as two's-complement signed integers to select the smaller value; source/destination overlap reads the values before writeback.
RV32/RV64, requiring Zbb 1.0; 32-bit R-type encoding with no immediate operand.
BZbbBit ManipulationInteger Operation
Instruction Behavior
MIN is a Zbb integer min/max instruction. It compares x[rs1] and x[rs2] as signed values and writes the original XLEN-bit value that is smaller under that ordering to rd.
MIN Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
min
,
,
Execution Context
Assumes RV32/RV64 with Zbb enabled, fixed initial register values, and PC=0x2000; instruction fetch succeeds and there are no asynchronous interrupts. These educational steps do not represent processor cycles.
a6(x16)
0xFFFFFFF0
sp(x2)
0x00000002
31..25
24..20
19..15
14..12
11..7
6..0
0000101
funct7
00010
rs2
10000
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x0A2842B3
opcode
0110011 -> OP
funct3
100 -> MIN
funct7
0000101 -> Zbb MIN/MAX selector
rd / rs1 / rs2
t0(x5) / a6(x16) / sp(x2)
integer comparison and selection
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0A2842B3
syntax : min t0(x5), a6(x16), sp(x2)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
MIN selects between rs1 and rs2 using signed ordering and returns the selected original XLEN-bit pattern, not a comparison bit.
Forms with U use unsigned ordering; forms without U use two's-complement signed ordering.
MIN operands and result are XLEN-wide integer-register values.
Common Usage Scenarios
Integer Comparison
Understand this scenario with real code like «min x10, x11, x12 ; x10 = signed_min(x11, x12)».
Integer Min/Max
Understand this scenario with real code like «min x10, x11, x12 ; x10 = signed_min(x11, x12)».
Pre-Use Checklist
Syntax Check
- RV32/RV64 requires enabled Zbb 1.0; register operands select x0–x31.
- Syntax has only rd, rs1 and rs2, with no rs3 or immediate operand.
Semantic Check
- MIN selects between rs1 and rs2 using signed ordering and returns the selected original XLEN-bit pattern, not a comparison bit.
- Overlapping operands read values before writeback; x0 is always zero and writes to x0 are discarded.
Pitfalls / Common Confusions
MIN uses signed comparison; use MINU for unsigned comparisons.
The result is the selected original register value, not Boolean 0/1.
MIN and MINU differ only in comparison signedness; the selected original bit pattern is written.
FAQ
How do I choose between MIN and MINU?
Use the non-U form for signed two's-complement ordering; use the U form when data is ordered as unsigned.