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PREFETCH.R

RISC-V PREFETCH.R Instruction Details

Instruction ManualI-type

data-read prefetch hint (Zicbop).

Instruction Syntax

prefetch.r offset(base)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicbopCache & Sync
Related Search Terms
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Instruction Behavior

PREFETCH.R is a Zicbop cache-block prefetch HINT indicating that the cache block at the effective address formed by rs1 plus sign-extended imm[11:0] is likely to be used for data read soon. The immediate requires imm[4:0]=0; an implementation may cache a copy in an appropriate cache to improve latency, but is not required to do so.

Quick Understanding & Search Notes

PREFETCH.R is a CMO cache-block prefetch hint; it locates a cache block by effective address but is not an ordinary load/store.

prefetch.* requires imm[4:0]=0 and an implementation may choose not to prefetch.
CBO.INVAL/CLEAN/FLUSH executability is controlled by environment configuration.
RISC-V Unprivileged ISA Manual: CMO cache-block operation extensions

Common Usage Scenarios

Cache & Hints

Understand this scenario with real code like «prefetch.r offset(base)».

Code Optimization

Understand this scenario with real code like «prefetch.r offset(base)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a HINT; implementations may ignore it without changing architectural correctness.
The effective address is rs1 plus sign-extended imm[11:0], and imm[4:0] must be zero.
Prefetch gives no memory-ordering, completion, or synchronization guarantee.

FAQ

Is PREFETCH.R equivalent to a fence?

No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.

Must the address for PREFETCH.R be cache-block aligned?

prefetch locates the block with base+offset and requires low 5 offset bits to be zero; the effective address follows the official rule.