Is PREFETCH.R equivalent to a fence?
No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.
PREFETCH.R
RISC-V PREFETCH.R Instruction Details
Instruction ManualI-typedata-read prefetch hint (Zicbop).
Instruction Syntax
prefetch.r offset(base)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicbopCache & Sync
Instruction Behavior
PREFETCH.R is a Zicbop cache-block prefetch HINT indicating that the cache block at the effective address formed by rs1 plus sign-extended imm[11:0] is likely to be used for data read soon. The immediate requires imm[4:0]=0; an implementation may cache a copy in an appropriate cache to improve latency, but is not required to do so.
PREFETCH.R Decode And Cache-Block Animation
Shows the official CMO/prefetch encoding, offset(base) operands, effective-address-to-cache-block selection, and ISA-visible effects.
offset
base
prefetch.r()
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0000010
offset[11:5]
00001
prefetch op
01011
rs1
110
funct3=ORI
00000
offset[4:0]=0
0010011
OP-IMM
Cache-Block Data Path
instruction
0x0415E013
opcode
0010011 -> OP-IMM hint
operation
00001 -> PREFETCH.R
funct3
110 -> ORI hint form
offset/base
64(a1(x11))
effective addr
0x0000000000001018 + 0x0000000000000040 = 0x0000000000001058
cache block
0x0000000000001040..0x000000000000107F
operation
hint that the cache block is likely to be used for data read soon
complete
hint issued; may be ignored
Current Step
Receive the 32-bit PREFETCH.R encoding
PREFETCH.R uses a 32-bit encoding; the animation starts by splitting the official fields.
encoding: 0x0415E013
syntax : prefetch.r 64(a1(x11))
effect : hint that the cache block is likely to be used for data read soon
Cache-Block Selection View
base
0x0000000000001018
EA
0x0000000000001058
target block
0x0000000000001040..0x000000000000107F
The example cache-block size is 64 bytes only to show how the address selects a block; the real size is discovered from the execution environment and is not fixed at 64 bytes.
This animation shows only architectural semantics from the RISC-V CMO extension: the effective address selects a cache block, execution can be environment-controlled, and prefetch is an ignorable HINT; it does not model concrete cache state, cache-line size, bus transactions, timing, or performance.
Quick Understanding & Search Notes
PREFETCH.R is a CMO cache-block prefetch hint; it locates a cache block by effective address but is not an ordinary load/store.
prefetch.* requires imm[4:0]=0 and an implementation may choose not to prefetch.
PREFETCH.R is only a data-read prefetch hint and provides no completion, memory-ordering, or synchronization semantics.
Common Usage Scenarios
Cache & Hints
Understand this scenario with real code like «prefetch.r offset(base)».
Code Optimization
Understand this scenario with real code like «prefetch.r offset(base)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This is a HINT; implementations may ignore it without changing architectural correctness.
The effective address is rs1 plus sign-extended imm[11:0], and imm[4:0] must be zero.
Prefetch gives no memory-ordering, completion, or synchronization guarantee.
FAQ
Must the address for PREFETCH.R be cache-block aligned?
prefetch locates the block with base+offset and requires low 5 offset bits to be zero; the effective address follows the official rule.