Is PREFETCH.R equivalent to a fence?
No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.
PREFETCH.R
RISC-V PREFETCH.R Instruction Details
Instruction ManualI-typedata-read prefetch hint (Zicbop).
Instruction Syntax
prefetch.r offset(base)
base / rs1: integer base register x0–x31; x0 always reads zero. The base need not be cache-block aligned.
offset: a sign-extended 12-bit byte displacement with five low zero bits; encodable multiples of 32 range from -2048 through 2016. The effective address wraps to XLEN.
There is no result register. Bits 11..7 are fixed to 00000 as offset[4:0]; bits 31..25 hold offset[11:5], while bits 24..20 are the fixed I/R/W operation selector.
ZicbopCache & Sync
Instruction Behavior
PREFETCH.R is a Zicbop cache-block prefetch HINT indicating that the cache block at the effective address formed by rs1 plus sign-extended imm[11:0] is likely to be used for data read soon. The immediate requires imm[4:0]=0; an implementation may cache a copy in an appropriate cache to improve latency, but is not required to do so.
PREFETCH.R Decode And Cache-Block Animation
Shows the official CMO/prefetch encoding, offset(base) operands, effective-address-to-cache-block selection, and ISA-visible effects.
offset
base
prefetch.r()
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0000010
offset[11:5]
00001
prefetch op
01011
rs1
110
funct3=ORI
00000
offset[4:0]=0
0010011
OP-IMM
Cache-Block Data Path
instruction
0x0415E013
opcode
0010011 -> OP-IMM hint
operation
00001 -> PREFETCH.R
funct3
110 -> ORI hint form
offset/base
64(x11)
effective addr
0x0000000000001018 + 0x0000000000000040 = 0x0000000000001058
cache block
physical cache block selected after translation (not modeled)
hint
hint that the cache block is likely to be used for data read soon
complete
hint issued; may be ignored
Current Step
Receive the 32-bit PREFETCH.R encoding
PREFETCH.R uses a 32-bit encoding; the animation starts by splitting the official fields.
encoding: 0x0415E013
syntax : prefetch.r 64(x11)
effect : hint that the cache block is likely to be used for data read soon
Cache-Block Selection View
base
0x0000000000001018
EA
0x0000000000001058
physical cache block
selected after translation (not modeled)
The effective address is translated before selecting a physical cache block; this animation does not assume a virtual-to-physical mapping or cache-block size.
This animation shows only architectural semantics from the RISC-V CMO extension: the effective address is translated before a cache block is selected, CBO execution can be environment-controlled, and prefetch is an ignorable HINT; it does not model concrete cache state, physical mappings, cache-line size, bus transactions, timing, or performance.
Quick Understanding & Search Notes
PREFETCH.R is a CMO cache-block prefetch hint; it locates a cache block by effective address but is not an ordinary load/store.
Zicbop supports RV32/RV64. ORI HINT encoding: opcode=0010011, funct3=110, offset[4:0]=0; bits 24..20 select I/R/W with 00000/00001/00011.
PREFETCH.R is only a data-read prefetch hint and provides no completion, memory-ordering, or synchronization semantics; denied access raises no exception, and translation neither checks nor sets accessed or dirty bits.
Common Usage Scenarios
Cache & Hints
Understand this scenario with real code like «prefetch.r 64(x11)».
Code Optimization
Understand this scenario with real code like «prefetch.r 64(x11)».
Pre-Use Checklist
Syntax Check
- Verify RV32/RV64 Zicbop; offset(base) uses an integer base register and an offset that is a multiple of 32 in -2048..2016.
- There is no result register; bits 11..7 fix offset[4:0]=00000. Base x0 reads zero, and the base need not be cache-block aligned.
Semantic Check
- Prefetch is an ignorable HINT with no completion, memory-ordering, or synchronization guarantee.
- Translate the address to select a physical cache block. Denied access raises no exception and accesses neither caches nor memory; translation does not check or set accessed/dirty bits.
Pitfalls / Common Confusions
This is a HINT; implementations may ignore it without changing architectural correctness.
The effective address is rs1 plus sign-extended imm[11:0], and imm[4:0] must be zero.
Prefetch gives no memory-ordering, completion, or synchronization guarantee; when access is not permitted, it raises no exception and accesses neither caches nor memory.
FAQ
Must the address for PREFETCH.R be cache-block aligned?
No. The offset is a multiple of 32 in -2048..2016; the base need not be aligned. Add the sign-extended offset to the base, wrap to XLEN, then translate the effective address to select the physical cache block.