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SSPOPCHK

RISC-V SSPOPCHK Instruction Details

Instruction ManualSYSTEM (MOP.R.28)

SSPOPCHK reads the shadow return address at ssp and checks it against x1/x5.

Instruction Syntax

sspopchk rs1
Operand Breakdown
This is a SYSTEM (MOP.R.28)-format instruction. Confirm operand positions based on the assembly syntax.
ZicfissSecurity Mechanisms
Related Search Terms
sspopchk instructionRISC-V sspopchksspopchk syntaxsspopchk encodingsspopchk shadow-stack pop checksspopchk CFIsspopchk shadow stack

Instruction Behavior

Beginner view: SSPOPCHK loads the shadow return address at ssp and compares it bit-for-bit with x1 or x5. A mismatch raises a software-check exception; on success ssp advances by XLEN/8.

SSPOPCHK Decode & Execute Animation

Shows only specification-defined encodings, conditions, and architectural state.

sspopchk x1
Execution Context
Instruction Encoding
31..20
MOP.R.28
110011011100
19..15
rs1
x1
14..12
funct3
100
11..7
rd
00000
6..0
opcode
SYSTEM
Decode fixed fields
ssp=0x0000000000002000, x[x1]=0x0000000012345678, mem[ssp]=0x0000000012345678
ssp <- 0x0000000000002008
Architectural state has not been committed.

Quick Understanding & Search Notes

SSPOPCHK is a Zicfiss shadow-stack check; xSSE and the access result determine comparison and ssp update.

Shadow-stack operations implicitly use ssp and XLEN width.
Do not mistake MOP compatibility for always-active security checks; inactive cases may degrade to no-op or zero-result behavior.
RISC-V Unprivileged ISA Manual: Control-Flow IntegrityRISC-V Unprivileged ISA Manual: Zimop/Zcmop May-Be-Operations

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «sspopchk x1».

Data Loading

Understand this scenario with real code like «sspopchk x1».

Resource Management

Understand this scenario with real code like «sspopchk x1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is SYSTEM (MOP.R.28).
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Only x1 and x5 are supported compared link-register operands.
Zicfiss depends on the Zicsr, Zimop, and Zaamo extensions.
A shadow-stack value mismatch raises a software-check exception.
A store/AMO access-fault has priority over software-check; if the implicit ssp load raises a store/AMO page-fault or guest-page-fault, it is not compared and ssp is not updated.
If ssp is not XLEN-aligned, SSPOPCHK raises a store/AMO access-fault.
The accessed memory must be idempotent and PMP must allow read/write access; otherwise it raises a store/AMO access-fault.
Trap behavior depends on privilege level, environment configuration CSRs, and page-table/memory attributes.
ssp is incremented by XLEN/8 only after the load succeeds and the comparison passes.
SSPOPCHK/C.SSPOPCHK increment ssp only after the load succeeds and comparison passes.

FAQ

What happens if the related CFI feature is inactive for SSPOPCHK?

Zicfiss instructions degrade according to the official Zimop/Zcmop-compatible behavior and do not perform shadow-stack checks or updates.

What official rule defines SSPOPCHK?

The Control-Flow Integrity chapter of the RISC-V Unprivileged ISA defines LPAD, SSPUSH, SSPOPCHK, SSRDP, and SSAMOSWAP.