Can VCLZ.V always use a v0.t mask?
It can use v0.t; omitting it gives vm=1. With vm=0, v0 is the EEW=1 mask, so a normal data source or destination cannot also reuse v0; that encoding is reserved.
VCLZ.V
RISC-V VCLZ.V Instruction Details
Instruction ManualV-typeVector count leading zeros: count leading zero bits in each element
Instruction Syntax
vclz.v vd, vs2, vm
vd, vs2 select v0–v31 with EEW=SEW and EMUL=LMUL. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01100[19:15] (fixed selector, not a source register), funct3=010, vd[11:7], opcode=1010111.
Zvbb supports SEW=8/16/32 with Zve32x; Zve64x also provides 64. Count consecutive zeros from the most-significant bit; zero input returns SEW.
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
ZvbbVector Bit Manipulation
Instruction Behavior
vclz.v is the Zvbb vector count-leading-zeros instruction. Counts leading zero bits in each SEW element, writing the count to the corresponding destination element. Zve32x supports SEW=8/16/32; Zve64x also supports SEW=64.
VCLZ.V Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
010010
25
vm
1
24..20
vs2
01000
19..15
vs1 fixed
01100
14..12
funct3
010
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct6=010010, funct3=010, Zvbb
v4[0] <- pending
Quick Understanding & Search Notes
vclz.v is the Zvbb vector count-leading-zeros instruction. Counts leading zero bits in each SEW element, writing the count to the corresponding destination element. Zve32x supports SEW=8/16/32; Zve64x also supports SEW=64.
Each element returns the number of leading zero bits from the most-significant bit; an all-zero element returns SEW.
Zvbb: Zve32x supports SEW=8/16/32; Zve64x also supports SEW=64.
Process only mask-enabled elements where vstart≤i<vl. When vstart≥vl (including vl=0), no destination elements update; successful completion resets vstart.
Vector Execution Context
vd, vs2 select v0–v31 with EEW=SEW and EMUL=LMUL. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01100[19:15] (fixed selector, not a source register), funct3=010, vd[11:7], opcode=1010111.
Zvbb supports SEW=8/16/32 with Zve32x; Zve64x also provides 64. Count consecutive zeros from the most-significant bit; zero input returns SEW.
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Common Usage Scenarios
Per-element bit operation example
With the listed extension and vector state enabled, legal vtype, LMUL=1, VLEN≥128, vl=1, vstart=0 and no mask: SEW=32, v8[0]=0x00000001: clz32=31, written to v4[0].
Pre-Use Checklist
Syntax Check
- vd, vs2 select v0–v31 with EEW=SEW and EMUL=LMUL. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
- 32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01100[19:15] (fixed selector, not a source register), funct3=010, vd[11:7], opcode=1010111.
Semantic Check
- Zvbb supports SEW=8/16/32 with Zve32x; Zve64x also provides 64. Count consecutive zeros from the most-significant bit; zero input returns SEW.
- Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
- Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Pitfalls / Common Confusions
Result is count (0..SEW), not a bit position index. All-zero element returns SEW.
FAQ
What determines the element width for VCLZ.V?
Zvbb: Zve32x supports SEW=8/16/32; Zve64x also supports SEW=64.