Can VCLZ.V always use a v0.t mask?
It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.
VCLZ.V
RISC-V VCLZ.V Instruction Details
Instruction ManualR-typeVector count leading zeros: count leading zero bits in each element
Instruction Syntax
vclz.v vd, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbbVector Bit Manipulation
Instruction Behavior
vclz.v is the Zvbb vector count-leading-zeros instruction. Counts leading zero bits in each SEW element, writing the count to the corresponding destination element. Supports all SEW.
Quick Understanding & Search Notes
VCLZ.V is a Zvbb vector instruction for vector count leading zeros. This page is checked against the official vector crypto extension and V-extension execution model.
Each element returns the number of leading zero bits from the most-significant bit; an all-zero element returns SEW.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vclz.v vd, vs2».
Vector Acceleration
Understand this scenario with real code like «vclz.v vd, vs2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Result is count (0..SEW), not a bit position index. All-zero element returns SEW.
FAQ
What determines the element width for VCLZ.V?
The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.