Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VLOXEI64.V
RISC-V VLOXEI64.V Instruction Details
Instruction ManualV-typeUse x[rs1] plus 64-bit unsigned byte offsets from vs2 for ordered indexed loads.
Instruction Syntax
vloxei64.v vd, (rs1), vs2, vm
Operand Breakdown
vd: destination vector register group receiving loaded active elements.
rs1: integer base-address register; unit-stride forms read elements from consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryIndexed Vector Load
Instruction Behavior
VLOXEI64.V is a RISC-V V-extension ordered indexed vector load instruction. Each active element forms its address from x[rs1] plus the address-width offset from vs2[i]; ei64 is the 64-bit index EEW, so the index is an unsigned byte offset, not an element number. A narrower index is zero-extended to XLEN, while an index wider than XLEN uses only its least-significant XLEN bits. The ordered form is observed in element order for address spaces that require element access order. With vm=0, elements disabled by v0.t do not access memory.
VLOXEI64.V Decode And Execute Animation
Decode the 64-bit indexed load, then compute each element address as x[rs1] + vs2[i].
Instruction input
vloxei64.v
Execution context: index EEW=64, data SEW=32, index EEW and XLEN are both 64, so the full index value is used, ordered indexed accesses proceed in element order and obey RVWMO at the element level, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Encoding fieldsvloxei64.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
11
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
111
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + vs2[i]
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x0000000000000001
0x0000000000000004
0x0000000000000007
0x000000000000000a
0x000000000000000d
0x0000000000000010
0x0000000000000013
0x0000000000000016
0x0000000000000019
0x000000000000001c
0x000000000000001f
0x0000000000000022
0x0000000000000025
0x0000000000000028
0x000000000000002b
0x000000000000002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
mem
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLOXEI64.V uses vs2 as byte offsets, not element numbers; the ordered form is for cases where observable access order matters.
Index EEW=64; loaded data elements use the current SEW, and register-group use is constrained by data SEW/LMUL together with index EEW.
Ordered indexed loads observe accesses in element order; offsets are unsigned byte offsets.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Vector Execution Context
When reading VLOXEI64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Ordered indirect reads
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vloxei64.v v1, (a0), v2».
Device or side-effecting address spaces
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vloxei64.v v1, (a0), v2».
Sparse table reads
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vloxei64.v v1, (a0), v2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
ei64 is the index EEW, not the SEW of the loaded data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; addressing zero-extends a narrower index to XLEN and uses the least-significant XLEN bits of a wider index. It is not x[rs1] + i * EEW and not an element number.
The ordered indexed form only states element-order observation; do not read it as a cache, pipeline, or bus implementation model.
With vm=0, elements disabled by v0.t perform no memory read and must not be shown as writing zero.
A naturally aligned active access must not raise an address-misaligned exception; an EEI defines whether an unaligned access completes or raises an address-misaligned or access-fault exception.
FAQ
What unit is used for VLOXEI64.V address offsets?
Indexed-load vs2 elements are unsigned byte offsets.
How does VLOXEI64.V handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.