VLOXEI64.V

RISC-V VLOXEI64.V Instruction Details

Q: What unit is used for VLOXEI64.V address offsets?

Indexed-load vs2 elements are unsigned byte offsets.

Q: How does VLOXEI64.V handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.

Q: Can RV32 V execute VLOXEI64.V?

It is not supported by standard V. With XLEN=32, V does not support index EEW=64; this page’s animation fixes RV64.

Instruction ManualV-type

On RV64 V, load with ordered 64-bit byte offsets from vs2 plus x[rs1]; RV32 V does not support ei64.

Instruction Syntax

vloxei64.v vd, (rs1), vs2, vm

Operand Breakdown

Syntax: vloxei64.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.

ei64 fixes index EEW=64; data EEW=SEW and EMUL=LMUL, while index EMUL=(64/SEW)×LMUL. The index width must be supported, EMUL in 1/8..8, and group starts legal; different-EEW overlap must also satisfy low/high-end restrictions.

Address is x[rs1] plus the vs2[i] byte offset: the general rule zero-extends narrower indices or takes low XLEN bits of wider ones. V does not support index EEW=64 on RV32; this ei64 page uses RV64. Ordered accesses obey RVWMO in element order, without cache or cycle guarantees.

Require enabled V/VS and valid vtype. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and legal different-EEW overlap forces ma/ta. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.

VVector MemoryIndexed Vector Load

Related Search Terms

VLOXEI64.V instruction RISC-V VLOXEI64.V vloxei64.v syntax vloxei64.v encoding RVV indexed load ei64 index ordered indexed load

Instruction Behavior

VLOXEI64.V is a RISC-V V-extension ordered indexed vector load. ei64 sets index EEW=64, while SEW selects data width. V supports this form on RV64 but does not support 64-bit index EEW on RV32; the general index-truncation rule does not make this an RV32 V instruction. On RV64, each active element uses x[rs1]+vs2[i], with an unsigned byte offset rather than an element number. Ordered accesses obey RVWMO in element order; with vm=0, elements disabled by v0.t do not access memory.

VLOXEI64.V Decode And Execute Animation

Decode the 64-bit indexed load, then compute each element address as x[rs1] + vs2[i].

Instruction input

vloxei64.v

vdVector register v0-v31rs1Integer base-address registervs2Index vector register v0-v31vmexecution mask control

VLSEWx[rs1]vs2 index bytes (64)0..0xffffffffffffffff, unsigned byte offsetsmemory elements0..0xffffffff, comma-separatedv0 mask bits0/1 only, length equals VL

Execution context: index EEW=64, data SEW=32, index EEW and XLEN are both 64, so the full index value is used, ordered indexed accesses proceed in element order and obey RVWMO at the element level, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.

V does not support index EEW=64 on RV32; this animation fixes RV64 and offers no RV32 execution path. The generic low-XLEN rule for wider indices does not override this support limit.

Teaching context: XLEN=64, VLEN=4096, SEW=32, LMUL=m1, VLMAX=128, index EMUL=2, valid vtype, enabled VS, vstart=0, and ta/ma. All selected accesses are assumed successful; traps are not modeled. Unaligned accesses apply only where the environment supports them. rs1=x0 fixes the base at 0. The memory elements input gives the value observed by each active read, allowing memory to change between accesses; it is not a static byte-memory image. Per-element steps do not represent processor cycles; ordered accesses obey RVWMO in element order. Inactive/tail “-” means the result is not shown and may retain the old value or become all ones. VL=0 leaves the destination unchanged; normal completion resets vstart=0.

Encoding fieldsvloxei64.v / LOAD-FP

31..29

000

mew

27..26

mop

24..20

vs2

10000

19..15

rs1

01010

14..12

width

111

11..7

vd/vs3

01000

6..0

opcode

0000111

Address and data pathaddr[i] = 0x8000 + vs2[i]

i=0

i=1

i=2

i=3

i=4

i=5

i=6

i=7

i=8

i=9

i=10

i=11

i=12

i=13

i=14

i=15

vs2 byte offset

0x0000000000000001

0x0000000000000004

0x0000000000000007

0x000000000000000a

0x000000000000000d

0x0000000000000010

0x0000000000000013

0x0000000000000016

0x0000000000000019

0x000000000000001c

0x000000000000001f

0x0000000000000022

0x0000000000000025

0x0000000000000028

0x000000000000002b

0x000000000000002e

addr

0x8001

0x8004

0x8007

0x800a

0x800d

0x8010

0x8013

0x8016

0x8019

0x801c

0x801f

0x8022

0x8025

0x8028

0x802b

0x802e

mem

0x00000101

0x00000202

0x00000303

0x00000404

0x00000505

0x00000606

0x00000707

0x00000808

0x00000909

0x00000a0a

0x00000b0b

0x00000c0c

0x00000d0d

0x00000e0e

0x00000f0f

0x00001010

active

...

Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VLOXEI64.V uses vs2 as byte offsets, not element numbers; the ordered form is for cases where observable access order matters.

Index EEW=64; loaded data elements use the current SEW, and register-group use is constrained by data SEW/LMUL together with index EEW.

Ordered indexed loads observe accesses in element order; offsets are unsigned byte offsets.

vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.

V supports ei64 on RV64; RV32 V does not support index EEW=64. The generic low-XLEN rule for wider indices does not override this extension limit.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120), Chapter 31

Vector Execution Context

Syntax: vloxei64.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Ordered indirect reads

Assume RV64 V; enabled V/VS, supported data/index widths, VLEN≥128, x10=0x8000, x11=4, and successful memory accesses; vsetvli sets vl=4, vstart=0, ta/ma. e32,m1; v2 byte offsets=[0,8,16,24]; addresses=[0x8000,0x8008,0x8010,0x8018]; memory values=[10,20,30,40] → v1=[10,20,30,40]. Omitting v0.t makes this unmasked. Agnostic elements may retain old values or become all ones; tails are not guaranteed zero.

Device or side-effecting address spaces

Sparse table reads

Pre-Use Checklist

Syntax Check

Syntax: vloxei64.v vd, (rs1), vs2[, v0.t]; omitted v0.t gives vm=1 and included v0.t gives vm=0. vd is a vector group, rs1 an integer base, with base 0 for rs1=x0.
ei64 fixes index EEW=64; data EEW=SEW and EMUL=LMUL, while index EMUL=(64/SEW)×LMUL. The index width must be supported, EMUL in 1/8..8, and group starts legal; different-EEW overlap must also satisfy low/high-end restrictions.

Semantic Check

Address is x[rs1] plus the vs2[i] byte offset: the general rule zero-extends narrower indices or takes low XLEN bits of wider ones. V does not support index EEW=64 on RV32; this ei64 page uses RV64. Ordered accesses obey RVWMO in element order, without cache or cycle guarantees.
Require enabled V/VS and valid vtype. Only elements with vstart≤i<vl and enabled masks access memory; masked vd cannot overlap v0. Prestart stays unchanged, inactive/tail follow vma/vta, and legal different-EEW overlap forces ma/ta. VL=0 or vstart≥vl updates no destination; normal completion resets vstart=0 and leaves vl unchanged.

Pitfalls / Common Confusions

ei64 is the index EEW, not the SEW of the loaded data; data element width still comes from current vtype.

V supports ei64 on RV64, not RV32. The general rule zero-extends narrower indices and takes low XLEN bits of wider indices, but does not override an extension’s supported index EEWs.

The ordered indexed form only states element-order observation; do not read it as a cache, pipeline, or bus implementation model.

With vm=0, elements disabled by v0.t perform no memory read and must not be shown as writing zero.

An unaligned vector element access may transfer successfully or raise an address-misaligned exception on that element; vector and scalar misalignment support are independent.

FAQ

What unit is used for VLOXEI64.V address offsets?