Does ZIP access memory?
No. It only rearranges bit fields or performs register lookup within integer registers.
ZIP
RISC-V ZIP Instruction Details
Instruction ManualI-typeRV32 bit interleave (Zbkb), RV32-only.
Instruction Syntax
zip rd, rs1
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZbkbBit Manipulation
Instruction Behavior
ZIP (Zbkb, RV32-only) interleaves the low and high halves of the source register into the destination: for i=0..15, rd[2*i]=rs1[i] and rd[2*i+1]=rs1[i+16]. It is the inverse of UNZIP and is useful for SHA3 bit interleaving on 32-bit architectures.
Quick Understanding & Search Notes
ZIP is a Zbkb cryptographic bit-manipulation instruction; this page follows the official B-extension operation.
The official encoding and semantics are RV32-only.
These instructions rearrange bit/byte fields and do not access memory.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «zip a0, a1».
Logical Operations
Understand this scenario with real code like «zip a0, a1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
ZIP is defined only on RV32; there is no RV64 form.
Even bits come from the source low half and odd bits from the source high half; do not confuse it with byte shuffle.
This instruction is RV32-only; there is no RV64 form.
FAQ
Which extension contains ZIP?
It belongs to the Zbkb cryptographic bit-manipulation extension.