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RISC-V Topic Guide

Context Switch

RISC-V context switching is an OS or runtime save/restore convention that typically covers GPR and stack state, uses mstatus/sstatus FS, VS, and XS state to manage floating-point, vector, and extension context, and handles satp, ASIDs, and address-translation cache consistency when switching address spaces.

spras0-s11mstatusFSVSXSsatpASIDmscratchsscratchfcsrvlvtypestack

Core Concepts

sp

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ra

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s0-s11

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mstatus

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FS

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VS

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XS

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satp

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ASID

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mscratch

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sscratch

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fcsr

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vl

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vtype

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stack

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Related Entries

trap-handlinginterrupt-handlingexception-handlingvirtual-memoryprivilege-levelsfloating-point

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA ManualRISC-V Privileged Architecture ManualRISC-V Assembly Programmer's ManualRISC-V psABI Specification