RVOPcodeRISC-V Developer Reference

RISC-V Topic Guide

CSR Access

Learn how the Zicsr CSRRW/CSRRS/CSRRC and CSRRWI/CSRRSI/CSRRCI instructions atomically read and update CSRs, including CSR access permissions, conditional read/write rules, field side effects, and the privilege scope of common CSRs such as mstatus, mie, and fcsr.

CSRRWCSRRSCSRRCCSRRWICSRRSICSRRCImstatusmiefcsrCSR

Core Concepts

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

privilege-levels trap-handling exception-handling interrupt-handling floating-point virtual-memory

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification