RVOPcodeRISC-V Developer Reference

RISC-V Topic Guide

Exception Handling

RISC-V exception handling focuses on synchronous traps: mcause/scause cause codes, mtvec/stvec entries, mepc/sepc exception PCs, mtval/stval auxiliary information, medeleg delegation, and typical exceptions such as illegal instruction, breakpoint, ECALL, and page faults.

mcausescausemtvecstvecmepcsepcmtvalstvalMRETSRETmedelegECALLEBREAKpage fault

Core Concepts

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

trap-handling interrupt-handling system-call privilege-levels csr-access virtual-memory

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification