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RISC-V Topic Guide

Floating-Point

RISC-V F/D floating-point covers 32 floating-point registers f0-f31, IEEE 754-2008-compatible single/double-precision operations, floating-point loads/stores, conversions and comparisons, plus frm dynamic rounding mode and fflags accrued exception flags in fcsr.

FADD.SFSUB.SFMUL.DFDIV.DFSQRT.SFMADD.SFLWFSWFLDFSDFCVT.S.Wfcsrfrmfflags

Core Concepts

FADD.S

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FSUB.S

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FMUL.D

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FDIV.D

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FSQRT.S

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FMADD.S

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FLW

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FSW

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FLD

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FSD

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FCVT.S.W

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fcsr

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frm

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fflags

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Related Entries

calling-conventioncontext-switchcsr-accessvector-programmingfunction-callexception-handling

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA ManualRISC-V Privileged Architecture ManualRISC-V Assembly Programmer's ManualRISC-V psABI Specification