RVOPcodeRISC-V Developer Reference

RISC-V Topic Guide

Interrupt Handling

RISC-V interrupt handling covers mip/mie and sip/sie pending and enable CSRs, software/timer/external interrupt causes, global interrupt-enable bits in mstatus/sstatus, mideleg delegation, the WFI instruction, and platform or extension interrupt-controller interfaces such as PLIC and AIA.

mipmiesipsiemstatussstatusmidelegmtvecstvecWFIPLICAIA

Core Concepts

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

trap-handling exception-handling privilege-levels csr-access context-switch system-call

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification