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RISC-V Topic Guide

Memory Ordering

RISC-V memory ordering covers the RVWMO default memory consistency model, FENCE ordering of memory and I/O accesses, Zifencei FENCE.I instruction-fetch synchronization, A-extension aq/rl bits, and stronger ordering constraints provided by Ztso and FENCE.TSO.

RVWMOFENCEFENCE.IFENCE.TSOZtsoaqrlAMO aq/rlmemory modelI/O ordering

Core Concepts

RVWMO

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FENCE

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FENCE.I

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FENCE.TSO

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Ztso

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aq

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rl

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AMO aq/rl

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memory model

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I/O ordering

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Related Entries

atomic-operationsvirtual-memoryinterrupt-handlingcontext-switchcsr-accessbit-manipulation

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA ManualRISC-V Privileged Architecture ManualRISC-V Assembly Programmer's ManualRISC-V psABI Specification