RVOPcodeRISC-V Developer Reference

RISC-V Topic Guide

Privilege Levels

The RISC-V privileged architecture defines privilege modes including M, S, and U, and the Hypervisor extension adds HS behavior plus VS/VU virtual privilege modes; key topics include per-level CSRs, ECALL traps, MRET/SRET returns, mstatus/sstatus/hstatus state, and exception/interrupt delegation.

M-modeS-modeU-modeHS behaviorVS virtual modeVU virtual modemstatussstatushstatusECALLMRETSRETmedelegmidelegCSR

Core Concepts

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VS virtual mode

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VU virtual mode

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Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

trap-handling exception-handling interrupt-handling virtual-memory system-call csr-access

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification