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RISC-V Topic Guide

Stack Frame

RISC-V stack frames follow the psABI: sp is 16-byte aligned at procedure entry and remains aligned during execution, prologue/epilogue code typically allocates and frees stack space, saves ra and callee-saved registers when needed, and may use s0/fp to form an optional frame-pointer chain.

sprafps0s0-s11ADDISDLDSWLW16-byte alignmentstack frameprologueepilogue

Core Concepts

sp

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ra

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fp

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s0

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s0-s11

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ADDI

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SD

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LD

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SW

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LW

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16-byte alignment

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stack frame

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prologue

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epilogue

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Related Entries

function-callcalling-conventioncontrol-flowcompressed-codecontext-switchsystem-call

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA ManualRISC-V Privileged Architecture ManualRISC-V Assembly Programmer's ManualRISC-V psABI Specification