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RISC-V Topic Guide

Vector Programming

RISC-V V-extension vector programming centers on v0-v31 vector registers, vl/vtype/vlenb/vstart/vcsr CSRs, VSETVLI/VSETIVLI/VSETVL configuration, SEW/LMUL, mask and tail policies, and vector load/store, arithmetic, comparison, and reduction instructions.

VSETVLIVSETIVLIVSETVLvlvtypevlenbvstartv0-v31SEWLMULmasktail policyVLE8.VVADD.VVVREDSUM.VS

Core Concepts

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

floating-point memory-ordering context-switch calling-convention crypto-extensions bit-manipulation

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification