RVOPcodeRISC-V Developer Reference

RISC-V Topic Guide

Virtual Memory

RISC-V paged virtual memory covers satp MODE/ASID/PPN fields, Sv32/Sv39/Sv48/Sv57 translation schemes, PTE permissions and A/D bits, page-fault exceptions, MXR/SUM access control, and address-translation cache invalidation mechanisms such as SFENCE.VMA and SINVAL.VMA from the Svinval extension.

satpSFENCE.VMASINVAL.VMASv32Sv39Sv48Sv57page tablePTEASIDTLBMXRSUM

Core Concepts

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Find related instructions, registers, CSRs, or pseudo-instructions.

Related Entries

privilege-levels csr-access trap-handling exception-handling context-switch memory-ordering

Official References

RISC-V behavior on this topic should be checked against the official specifications; content additions should only use facts verifiable in these documents.

RISC-V Unprivileged ISA Manual RISC-V Privileged Architecture Manual RISC-V Assembly Programmer's Manual RISC-V psABI Specification