RISC-V hcontext CSR Register

Address 0x6A8Privilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hcontext is the Hypervisor-mode context CSR defined by Sdtrig.

Related Search Terms

hcontext CSR hcontext 0x6A8 hypervisor context value for debug/trace Hypervisor

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

RESERVED_ZERO63:14RO0 HCONTEXT13:0WARL

Field Map

Understand hcontext By Bit Fields

2 key fields

13:0

HCONTEXT

WARL

Alias of mcontext.hcontext. M-mode or HS-mode software may write a context number for triggers that fire only in that context; an implementation may tie any number of upper bits to zero.

HCONTEXT (bits 13:0) — Alias of mcontext.hcontext. M-mode or HS-mode software may write a context number for triggers that fire only in that context; an implementation may tie any number of upper bits to zero.

What This Field Controls

- Alias of mcontext.hcontext. M-mode or HS-mode software may write a context number for triggers that fire only in that context; an implementation may tie any number of upper bits to zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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XLEN-1:14

RESERVED_ZERO

RO0

Bits outside mcontext.hcontext in the current effective XLEN; they read as zero.

RESERVED_ZERO (bits XLEN-1:14) — Bits outside mcontext.hcontext in the current effective XLEN; they read as zero.

What This Field Controls

- Bits outside mcontext.hcontext in the current effective XLEN; they read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

hcontext is an optional Sdtrig CSR and alias of mcontext.hcontext[13:0]; it lets HS-mode set a value used by context-qualified triggers.

hcontext is optional only when the H extension is present, and implementing it also requires mcontext.

It is accessible in HS, M, and Debug Mode; with Smstateen, HS-mode access is controlled by mstateen0.CONTEXT (bit 57).

The CSR aliases mcontext.hcontext[13:0], its upper bits read as zero, and its field is WARL.

RISC-V Privileged Architecture Manual - CSR table RISC-V Debug Specification - Trigger Module Registers

What To Check First When Reading This CSR

- hcontext is an optional Hypervisor-level CSR that may be implemented only with the H extension; implementing it requires mcontext.
- It is accessible only in HS-mode, M-mode, and Debug Mode; if Smstateen is implemented, HS-mode access is controlled by mstateen0.CONTEXT (bit 57).

Risk Checks Before Writing

- Access it only when hcontext is implemented and the current mode is HS, M, or Debug; with Smstateen, HS-mode must also be permitted by mstateen0.CONTEXT.

Put It Back Into A Real Flow

Confirm that H and Sdtrig are implemented and that mcontext is also implemented.

In HS-mode, if Smstateen is implemented, confirm that mstateen0.CONTEXT permits access.

Update only hcontext[13:0] under its WARL rule and use it for context-qualified triggers.

FAQ

Can hcontext be accessed through a supervisor CSR alias?

No. hcontext is the HS-mode alias of mcontext.hcontext[13:0], not a VS supervisor CSR alias.