RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mcontext CSR Register

Address 0x7A8Privilege Machine/Debug modeAccess RW / XLENDebug trigger CSRs

mcontext is an optional XLEN-bit Machine/Debug context CSR; it must be implemented when hcontext is implemented.

Related Search Terms
mcontext CSRmcontext 0x7A8HCONTEXTSdtrig context
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:14RO0HCONTEXT13:0WARL
Field Map

Understand mcontext By Bit Fields

2 key fields
XLEN-1:14

Reserved

RO0

Reserved and reads as zero.

Reserved (bits XLEN-1:14) — Reserved and reads as zero.

What This Field Controls

  • - Reserved and reads as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

13:0

HCONTEXT

WARL

Context number; an implementation may tie any number of upper bits to zero. Without H, 6 bits on RV32 and 13 on RV64 are recommended; with H, 7 and 14 bits respectively are recommended.

HCONTEXT (bits 13:0) — Context number; an implementation may tie any number of upper bits to zero. Without H, 6 bits on RV32 and 13 on RV64 are recommended; with H, 7 and 14 bits respectively are recommended.

What This Field Controls

  • - Context number; an implementation may tie any number of upper bits to zero. Without H, 6 bits on RV32 and 13 on RV64 are recommended; with H, 7 and 14 bits respectively are recommended.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mcontext provides a Machine-mode trigger context number.

mcontext is accessible only in Machine mode and Debug mode.
mcontext is required when hcontext is implemented, and HCONTEXT is WARL.
RISC-V Privileged Architecture ManualRISC-V Debug Specification v1.0

What To Check First When Reading This CSR

  • - mcontext is mandatory when hcontext is implemented and optional otherwise; access to an unimplemented Trigger Module register raises an illegal-instruction exception.
  • - Only Machine mode and Debug mode may access mcontext.

Risk Checks Before Writing

  • - HCONTEXT is WARL; read it back after writing to determine the context number accepted by the implementation.

Put It Back Into A Real Flow

1

Confirm that mcontext is implemented.

2

Write and read back HCONTEXT.

3

Use the context number with trigger configurations supported by the target implementation.