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CSR Bit Fields

RISC-V tselect CSR Register

Address 0x7A0Privilege Machine/Debug modeAccess RW / XLENDebug trigger CSRs

tselect is an optional XLEN-bit WARL CSR that selects the trigger accessed through other Trigger Module registers.

Related Search Terms
tselect CSRtselect 0x7A0Sdtrig trigger selecttdata1 type
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
INDEX63:0WARL
Field Map

Understand tselect By Bit Fields

1 key fields
XLEN-1:0

INDEX

WARL

Selected trigger index. Accessible indices start at 0 and are contiguous; an unsupported index may read back differently or select a trigger whose type is 0.

INDEX (bits XLEN-1:0) — Selected trigger index. Accessible indices start at 0 and are contiguous; an unsupported index may read back differently or select a trigger whose type is 0.

What This Field Controls

  • - Selected trigger index. Accessible indices start at 0 and are contiguous; an unsupported index may read back differently or select a trigger whose type is 0.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

tselect chooses the trigger accessed by tdata1, tdata2, and tdata3.

Accessible trigger indices must start at 0 and be contiguous.
An unsupported index can read back differently or point to type 0.
RISC-V Privileged Architecture ManualRISC-V Debug Specification v1.0

What To Check First When Reading This CSR

  • - tselect is optional when no triggers are implemented; access to an unimplemented Trigger Module register raises an illegal-instruction exception.
  • - tselect is accessible only in Machine mode and Debug mode.

Risk Checks Before Writing

  • - An external debugger must restore tselect after modifying it.
  • - Read back tselect and tdata1 after writing to confirm that type is nonzero.

Put It Back Into A Real Flow

1

Write an index.

2

Read back tselect.

3

Read tdata1.type to confirm that the selected trigger exists.