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CSR Bit Fields

RISC-V tdata1 CSR Register

Address 0x7A1Privilege Machine/Debug modeAccess RW / XLENDebug trigger CSRs

tdata1 is an optional XLEN-bit trigger-control CSR providing type, Debug write protection, and trigger-specific data for the trigger selected by tselect.

Related Search Terms
tdata1 CSRtdata1 0x7A1Sdtrig TYPEDMODEWARL
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
TYPE63:60WARLDMODE59WARLDATA58:0WARL
Field Map

Understand tdata1 By Bit Fields

3 key fields
XLEN-1:XLEN-4

TYPE

WARL

Trigger type: 0 means no trigger at this tselect; 1 is a legacy SiFive address-match trigger that should not be implemented; 2=mcontrol, 3=icount, 4=itrigger, 5=etrigger, 6=mcontrol6, 7=tmexttrigger, and 12–14 are custom. Type 15 disables the trigger and ignores remaining bits except DMODE; other values are reserved.

TYPE (bits XLEN-1:XLEN-4) — Trigger type: 0 means no trigger at this tselect; 1 is a legacy SiFive address-match trigger that should not be implemented; 2=mcontrol, 3=icount, 4=itrigger, 5=etrigger, 6=mcontrol6, 7=tmexttrigger, and 12–14 are custom. Type 15 disables the trigger and ignores remaining bits except DMODE; other values are reserved.

What This Field Controls

  • - Trigger type: 0 means no trigger at this tselect; 1 is a legacy SiFive address-match trigger that should not be implemented; 2=mcontrol, 3=icount, 4=itrigger, 5=etrigger, 6=mcontrol6, 7=tmexttrigger, and 12–14 are custom. Type 15 disables the trigger and ignores remaining bits except DMODE; other values are reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
XLEN-5

DMODE

WARL

When 0, Debug and Machine mode may write the selected trigger's tdata; when 1, only Debug mode may write and writes from other modes are ignored. It is hard-wired to 0 when type=0 and writable only from Debug mode.

DMODE (bits XLEN-5) — When 0, Debug and Machine mode may write the selected trigger's tdata; when 1, only Debug mode may write and writes from other modes are ignored. It is hard-wired to 0 when type=0 and writable only from Debug mode.

What This Field Controls

  • - When 0, Debug and Machine mode may write the selected trigger's tdata; when 1, only Debug mode may write and writes from other modes are ignored. It is hard-wired to 0 when type=0 and writable only from Debug mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
XLEN-6:0

DATA

WARL

Trigger-specific data; hard-wired to 0 when type is 0.

DATA (bits XLEN-6:0) — Trigger-specific data; hard-wired to 0 when type is 0.

What This Field Controls

  • - Trigger-specific data; hard-wired to 0 when type is 0.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

tdata1 TYPE determines the selected trigger kind and how its remaining data bits are interpreted.

type=0 means no trigger, with the associated hard-wired-zero rules.
With DMODE=1, Machine-mode writes to tdata are ignored.
RISC-V Privileged Architecture ManualRISC-V Debug Specification v1.0

What To Check First When Reading This CSR

  • - tdata1 is optional when no triggers are implemented; access to an unimplemented Trigger Module register raises an illegal-instruction exception.
  • - tdata registers are accessible only in Machine mode and Debug mode.

Risk Checks Before Writing

  • - Writing 0 to tdata1 must disable the trigger; if multiple types are supported, hardware should change type to 15.
  • - All tdata registers follow write-any-read-legal semantics; read back after writing to confirm a supported configuration.

Put It Back Into A Real Flow

1

Select tselect.

2

Write 0 to tdata1 to disable the trigger.

3

Write tdata2/tdata3, then write and read back the target tdata1.