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CSR Bit Fields

RISC-V hip CSR Register

Address 0x644Privilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hip is a Hypervisor interrupt-pending CSR.

Related Search Terms
hip CSRhip 0x644hypervisor interrupt-pending bitsHypervisor
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
IMPLEMENTATION_DEFINED_INTERRUPTS63:16WARL/RO0RESERVED2:0Read-only zero
Field Map

Understand hip By Bit Fields

6 key fields
HSXLEN-1:16

IMPLEMENTATION_DEFINED_INTERRUPTS

WARL/RO0

Higher interrupt bits are implementation-defined; unimplemented or non-writable bits read as zero.

IMPLEMENTATION_DEFINED_INTERRUPTS (bits HSXLEN-1:16) — Higher interrupt bits are implementation-defined; unimplemented or non-writable bits read as zero.

What This Field Controls

  • - Higher interrupt bits are implementation-defined; unimplemented or non-writable bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:14,12,10:8,6:4,2:0

RESERVED

Read-only zero

Reserved bits in the standard portion read as zero.

RESERVED (bits 15:14,12,10:8,6:4,2:0) — Reserved bits in the standard portion read as zero.

What This Field Controls

  • - Reserved bits in the standard portion read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
13

SGEIP

Read-only

HS-level guest external interrupt pending; it is 1 iff the bitwise AND of hgeip and hgeie is nonzero in any bit.

SGEIP (bit 13) — HS-level guest external interrupt pending; it is 1 iff the bitwise AND of hgeip and hgeie is nonzero in any bit.

What This Field Controls

  • - HS-level guest external interrupt pending; it is 1 iff the bitwise AND of hgeip and hgeie is nonzero in any bit.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
11

VSEIP

Read-only

VS-level external interrupt pending; logical OR of hvip.VSEIP, the hgeip bit selected by hstatus.VGEIN, and any platform-specific VS-level external interrupt signal.

VSEIP (bit 11) — VS-level external interrupt pending; logical OR of hvip.VSEIP, the hgeip bit selected by hstatus.VGEIN, and any platform-specific VS-level external interrupt signal.

What This Field Controls

  • - VS-level external interrupt pending; logical OR of hvip.VSEIP, the hgeip bit selected by hstatus.VGEIN, and any platform-specific VS-level external interrupt signal.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
7

VSTIP

Read-only

VS-level timer interrupt pending; logical OR of hvip.VSTIP and, when Sstc is implemented, the timer signal from vstimecmp.

VSTIP (bit 7) — VS-level timer interrupt pending; logical OR of hvip.VSTIP and, when Sstc is implemented, the timer signal from vstimecmp.

What This Field Controls

  • - VS-level timer interrupt pending; logical OR of hvip.VSTIP and, when Sstc is implemented, the timer signal from vstimecmp.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
3

VSSIP

RW (hvip alias)

VS-level software interrupt pending; a writable alias of the same bit in hvip.

VSSIP (bit 3) — VS-level software interrupt pending; a writable alias of the same bit in hvip.

What This Field Controls

  • - VS-level software interrupt pending; a writable alias of the same bit in hvip.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hip is a Hypervisor interrupt-pending CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hip address, access class, and width are checked against the official CSR tables: 0x644, HRW, HSXLEN.
hip fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hip is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hip, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hip be accessed through a supervisor CSR alias?

Do not treat hip as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.