RISC-V hip CSR Register

Address 0x644Privilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hip is a Hypervisor interrupt-pending CSR.

Related Search Terms

hip CSR hip 0x644 hypervisor interrupt-pending bits Hypervisor

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

HYPERVISOR_INTERRUPT-PENDING_BITS63:0RW

Field Map

Understand hip By Bit Fields

1 key fields

HSXLEN-1:0

HYPERVISOR_INTERRUPT-PENDING_BITS

The hypervisor interrupt-pending bits of hip.

HYPERVISOR_INTERRUPT-PENDING_BITS (bits HSXLEN-1:0) — The hypervisor interrupt-pending bits of hip.

What This Field Controls

- The hypervisor interrupt-pending bits of hip.

Common Values

hip pending bits

0Not pending

Only for officially defined Hypervisor interrupt-pending bits: 0 means the corresponding interrupt is not pending; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Pending

Only for officially defined Hypervisor interrupt-pending bits: 1 means the corresponding interrupt is pending; delivery also depends on enable, global interrupt, delegation, virtualization, and interrupt-controller state.

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Official Basis & Search Notes

hip is a Hypervisor interrupt-pending CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hip address, access class, and width are checked against the official CSR tables: 0x644, HRW, HSXLEN.

hip fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

- hip is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hip, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hip be accessed through a supervisor CSR alias?

Do not treat hip as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.