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CSR Bit Fields

RISC-V hvip CSR Register

Address 0x645Privilege HypervisorAccess HRW / 64-bitHypervisor and virtualization CSRs

hvip is a virtual interrupt-pending bitmap for VS injection.

Related Search Terms
hvip CSRhvip 0x645RISC-V AIAvirtual interrupt pendingvirtual interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
AIA_VIRTUAL_INTERRUPTS63:13RW/RO0RESERVED1:0Read-only zero
Field Map

Understand hvip By Bit Fields

5 key fields
63:13

AIA_VIRTUAL_INTERRUPTS

RW/RO0

AIA virtual-interrupt bits. If the corresponding hvien bit is read-only zero, this hvip bit should be read-only zero; all other bits 13-63 must be writable.

AIA_VIRTUAL_INTERRUPTS (bits 63:13) — AIA virtual-interrupt bits. If the corresponding hvien bit is read-only zero, this hvip bit should be read-only zero; all other bits 13-63 must be writable.

What This Field Controls

  • - AIA virtual-interrupt bits. If the corresponding hvien bit is read-only zero, this hvip bit should be read-only zero; all other bits 13-63 must be writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11,9:7,5:3,1:0

RESERVED

Read-only zero

Reserved bits in the standard H-extension portion read as zero.

RESERVED (bits 12:11,9:7,5:3,1:0) — Reserved bits in the standard H-extension portion read as zero.

What This Field Controls

  • - Reserved bits in the standard H-extension portion read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
10

VSEIP

RW

Setting it to 1 asserts a VS-level external interrupt.

VSEIP (bit 10) — Setting it to 1 asserts a VS-level external interrupt.

What This Field Controls

  • - Setting it to 1 asserts a VS-level external interrupt.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
6

VSTIP

RW

Setting it to 1 asserts a VS-level timer interrupt.

VSTIP (bit 6) — Setting it to 1 asserts a VS-level timer interrupt.

What This Field Controls

  • - Setting it to 1 asserts a VS-level timer interrupt.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
2

VSSIP

RW

Setting it to 1 asserts a VS-level software interrupt.

VSSIP (bit 2) — Setting it to 1 asserts a VS-level software interrupt.

What This Field Controls

  • - Setting it to 1 asserts a VS-level software interrupt.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hvip is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hvip address, access class, and width are checked against the official CSR tables: 0x645, HRW, 64-bit.
AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.
Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture CSR chapterRISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

  • - hvip is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hvip, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hvip be accessed through a supervisor CSR alias?

Do not treat hvip as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hvip?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.