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CSR Bit Fields

RISC-V hpmcounter28h CSR Register

Address 0xC9CPrivilege UserAccess RO / RV32 high-half / 32-bitUser counters and performance-monitoring CSRs

hpmcounter28h is a Zihpm user-level read-only CSR that exists only when XLEN=32 and reads hpmcounter28 bits 63:32. Zihpm depends on Zicsr; the number, width, and counted events of implemented counters are platform-specific.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand hpmcounter28h By Bit Fields

0 key fields

What To Check First When Reading This CSR

  • - hpmcounter28h exists only when XLEN=32; accessing a high-half CSR when XLEN>32 raises an illegal-instruction exception.
  • - Zihpm provides up to 29 additional performance counters; the number, width, and events of implemented counters are platform-specific. An unimplemented counter access may raise an illegal-instruction exception or return a constant value.
  • - On privileged implementations with S-mode, U-mode reads require the HPM28 bits in both mcounteren and scounteren; without S-mode, mcounteren controls access in U-mode. When V=1, access is also subject to mcounteren and hcounteren; VU-mode also requires scounteren, and a clear hcounteren bit raises a virtual-instruction exception when the corresponding mcounteren bit is set.

Risk Checks Before Writing

  • - hpmcounter28h is read-only; writing a read-only CSR raises an illegal-instruction exception.

Put It Back Into A Real Flow

1

Read hpmcounter28h only on RV32.

2

Use it with the low 32-bit read of hpmcounter28.

3

Interpret the result using the platform-defined counter implementation, event configuration, and access controls.