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CSR Bit Fields

RISC-V hvictl CSR Register

Address 0x609Privilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hvictl is a AIA virtual interrupt delivery-control CSR.

Related Search Terms
hvictl CSRhvictl 0x609RISC-V AIAvirtual interrupt delivery controlvirtual interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:31Read-only zeroIPRIO7:0RW
Field Map

Understand hvictl By Bit Fields

8 key fields
HSXLEN-1:31

Reserved

Read-only zero

Reserved bits read as zero.

Reserved (bits HSXLEN-1:31) — Reserved bits read as zero.

What This Field Controls

  • - Reserved bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
30

VTI

RW

Virtual Trap Interrupt control. When 1, explicit VS-mode access to sip/sie (and siph/sieh on RV32) raises a virtual-instruction exception.

VTI (bit 30) — Virtual Trap Interrupt control. When 1, explicit VS-mode access to sip/sie (and siph/sieh on RV32) raises a virtual-instruction exception.

What This Field Controls

  • - Virtual Trap Interrupt control. When 1, explicit VS-mode access to sip/sie (and siph/sieh on RV32) raises a virtual-instruction exception.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
29:28

Reserved

Read-only zero

Reserved bits read as zero.

Reserved (bits 29:28) — Reserved bits read as zero.

What This Field Controls

  • - Reserved bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
27:16

IID

WARL

Virtual interrupt identity. At least 6 bits are implemented; if n bits are implemented, every value from 0 through 2^n-1 is supported.

IID (bits 27:16) — Virtual interrupt identity. At least 6 bits are implemented; if n bits are implemented, every value from 0 through 2^n-1 is supported.

What This Field Controls

  • - Virtual interrupt identity. At least 6 bits are implemented; if n bits are implemented, every value from 0 through 2^n-1 is supported.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:10

Reserved

Read-only zero

Reserved bits read as zero.

Reserved (bits 15:10) — Reserved bits read as zero.

What This Field Controls

  • - Reserved bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
9

DPR

RW

Default Priority Rank. For an hvictl-specified interrupt with VTI=1, selects its default rank relative to virtual SEI; ignored when IID=9.

DPR (bit 9) — Default Priority Rank. For an hvictl-specified interrupt with VTI=1, selects its default rank relative to virtual SEI; ignored when IID=9.

What This Field Controls

  • - Default Priority Rank. For an hvictl-specified interrupt with VTI=1, selects its default rank relative to virtual SEI; ignored when IID=9.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
8

IPRIOM

RW

IPRIO mode, controlling how IPRIO is reported in vstopi.

IPRIOM (bit 8) — IPRIO mode, controlling how IPRIO is reported in vstopi.

What This Field Controls

  • - IPRIO mode, controlling how IPRIO is reported in vstopi.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
7:0

IPRIO

RW

Virtual interrupt priority number; always the full 8 bits.

IPRIO (bits 7:0) — Virtual interrupt priority number; always the full 8 bits.

What This Field Controls

  • - Virtual interrupt priority number; always the full 8 bits.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hvictl is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hvictl address, access class, and width are checked against the official CSR tables: 0x609, HRW, HSXLEN.
AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.
Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture CSR chapterRISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

  • - hvictl is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hvictl, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hvictl be accessed through a supervisor CSR alias?

Do not treat hvictl as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hvictl?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.