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CSR Bit Fields

RISC-V hviprio1 CSR Register

Address 0x646Privilege HypervisorAccess HRW / 64-bitHypervisor and virtualization CSRs

hviprio1 is a first VS interrupt priority CSR.

Related Search Terms
hviprio1 CSRhviprio1 0x646RISC-V AIAVS interrupt priorityinterrupt priority
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
IPRIO1563:56WARL/RO0RESERVED7:0Read-only zero
Field Map

Understand hviprio1 By Bit Fields

6 key fields
7:0,23:16,39:32

RESERVED

Read-only zero

Priority bytes reserved for interrupts 0, 4, and 8; they read as zero.

RESERVED (bits 7:0,23:16,39:32) — Priority bytes reserved for interrupts 0, 4, and 8; they read as zero.

What This Field Controls

  • - Priority bytes reserved for interrupts 0, 4, and 8; they read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:8

IPRIO1

WARL/RO0

Unsigned priority number for interrupt 1 (supervisor software interrupt).

IPRIO1 (bits 15:8) — Unsigned priority number for interrupt 1 (supervisor software interrupt).

What This Field Controls

  • - Unsigned priority number for interrupt 1 (supervisor software interrupt).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31:24

IPRIO5

WARL/RO0

Unsigned priority number for interrupt 5 (supervisor timer interrupt).

IPRIO5 (bits 31:24) — Unsigned priority number for interrupt 5 (supervisor timer interrupt).

What This Field Controls

  • - Unsigned priority number for interrupt 5 (supervisor timer interrupt).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
47:40

IPRIO13

WARL/RO0

Unsigned priority number for interrupt 13 (counter overflow interrupt).

IPRIO13 (bits 47:40) — Unsigned priority number for interrupt 13 (counter overflow interrupt).

What This Field Controls

  • - Unsigned priority number for interrupt 13 (counter overflow interrupt).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
55:48

IPRIO14

WARL/RO0

Unsigned priority number for interrupt 14.

IPRIO14 (bits 55:48) — Unsigned priority number for interrupt 14.

What This Field Controls

  • - Unsigned priority number for interrupt 14.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:56

IPRIO15

WARL/RO0

Unsigned priority number for interrupt 15. All non-RO0 hviprio1/2 priority fields implement the same integer-bit count, at least max(IPRIOLEN, 6).

IPRIO15 (bits 63:56) — Unsigned priority number for interrupt 15. All non-RO0 hviprio1/2 priority fields implement the same integer-bit count, at least max(IPRIOLEN, 6).

What This Field Controls

  • - Unsigned priority number for interrupt 15. All non-RO0 hviprio1/2 priority fields implement the same integer-bit count, at least max(IPRIOLEN, 6).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hviprio1 is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hviprio1 address, access class, and width are checked against the official CSR tables: 0x646, HRW, 64-bit.
AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.
Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture CSR chapterRISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

  • - hviprio1 is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hviprio1, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hviprio1 be accessed through a supervisor CSR alias?

Do not treat hviprio1 as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hviprio1?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.