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CSR Bit Fields

RISC-V mhpmcounter10h CSR Register

Address 0xB8APrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mhpmcounter10h at 0xB8A is the RV32 machine high-half CSR for bits 63:32 of mhpmcounter10.

Related Search Terms
mhpmcounter10h CSRmhpmcounter10h 0xB8Amhpmcounter10 high halfRV32 HPM high half64-bit count
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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
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Understand mhpmcounter10h By Bit Fields

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Official Basis & Search Notes

mhpmcounter10h is the RV32 high-half access CSR for bits 63:32 of mhpmcounter10; its event meaning is still determined by mhpmevent10.

mhpmcounter10 is a WARL register with up to 64 bits of precision; RV32 accesses it through low/high halves mhpmcounter10/mhpmcounter10h.
On RV32, the high-half CSR accesses bits 63:32 and the low-half CSR accesses bits 31:0.
mhpmcounter10h does not select the event; event selection is in mhpmevent10.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

  • - mhpmcounter10h exists only on RV32; standard high-half CSR addresses are reserved when XLEN=64.
  • - mhpmcounter10 is a WARL register with up to 64 bits of precision; counter number, width, and events are platform-defined.
  • - mcountinhibit.HPM10 controls only whether mhpmcounter10 increments, not its accessibility.

Risk Checks Before Writing

  • - On RV32, writing mhpmcounter10h changes only bits 63:32 of mhpmcounter10.
  • - A legal implementation may make both mhpmcounter10 and its mhpmevent10 selector read-only zero.

Put It Back Into A Real Flow

1

On RV32, access mhpmcounter10h and mhpmcounter10 separately.

2

The high and low halves correspond to bits 63:32 and 31:0 of one WARL counter.

3

Use mhpmevent10 to determine the platform-selected event for the counter.

FAQ

Can mhpmcounter10h be accessed from any privilege level?

No. The official CSR table lists mhpmcounter10h as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Is mhpmcounter10h a separate counter?

No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter10.