RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mhpmcounter10h CSR Register

Address 0xB8APrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mhpmcounter10h at 0xB8A is the RV32 machine high-half CSR for bits 63:32 of mhpmcounter10.

Related Search Terms
mhpmcounter10h CSRmhpmcounter10h 0xB8Amhpmcounter10 high halfRV32 HPM high half64-bit count
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32COUNT_HI31:0RW
Field Map

Understand mhpmcounter10h By Bit Fields

1 key fields
31:0

COUNT_HI

RW

Upper 32 bits of the HPM count, corresponding to mhpmcounter10[63:32].

COUNT_HI (bits 31:0) — Upper 32 bits of the HPM count, corresponding to mhpmcounter10[63:32].

What This Field Controls

  • - Upper 32 bits of the HPM count, corresponding to mhpmcounter10[63:32].

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter10h is the RV32 high-half access CSR for bits 63:32 of mhpmcounter10; its event meaning is still determined by mhpmevent10.

The official counter is 64 bits; RV32 accesses it through low/high halves mhpmcounter10/mhpmcounter10h.
When reading an incrementing counter, avoid high/low half inconsistency across a carry.
mhpmcounter10h does not select the event; event selection is in mhpmevent10.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

  • - mhpmcounter10h is an RV32-only high-half CSR; when XLEN=64, read the full count through mhpmcounter10.
  • - When reading a 64-bit incrementing counter, use a stable high-low-high style sequence to avoid inconsistency across a 32-bit carry.
  • - The event source for mhpmcounter10 is still determined by mhpmevent10.

Risk Checks Before Writing

  • - Writing mhpmcounter10h changes only the upper 32 bits of mhpmcounter10; it is usually used only during initialization or sample reset.
  • - Avoid writing the high half independently while the low half mhpmcounter10 is being updated in a conflicting path.

Put It Back Into A Real Flow

1

On RV32, read mhpmcounter10h and mhpmcounter10 using a stable sequence.

2

Combine the high and low halves to form the 64-bit mhpmcounter10 count.

3

Use mhpmevent10 to interpret which event the count represents.

FAQ

Can mhpmcounter10h be accessed from any privilege level?

No. The official CSR table lists mhpmcounter10h as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Is mhpmcounter10h a separate counter?

No. It is only the RV32 access CSR for the upper 32 bits of mhpmcounter10.