RISC-V mhpmcounter10 CSR Register

Address 0xB0APrivilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter10 at 0xB0A is machine hardware performance-monitor counter 10, with up to 64 bits of precision for the event selected by mhpmevent10.

Related Search Terms

mhpmcounter10 CSR mhpmcounter10 0xB0A HPM counter 10 mhpmevent10 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter10 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent10; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent10 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent10; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent10 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent10; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent10 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter10 is machine HPM counter 10. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent10.

The official machine HPM mechanism defines mhpmcounter10 as a WARL counter with up to 64 bits of precision.

mhpmevent10 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter10h accesses bits 63:32; a legal implementation may make both mhpmcounter10 and mhpmevent10 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter10 is selected by mhpmevent10; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter10 view are controlled by mcounteren.HPM10; U-mode is additionally controlled by scounteren.HPM10.
- On RV32, mhpmcounter10h accesses bits 63:32 of mhpmcounter10.

Risk Checks Before Writing

- Writing mhpmcounter10 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM10 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent10 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent10 to select the platform-defined event to count.

Set mcountinhibit.HPM10 when needed to stop mhpmcounter10 from incrementing.

Read mhpmcounter10; on RV32, also read mhpmcounter10h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter10 be accessed from any privilege level?

No. The CSR table lists mhpmcounter10 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter10 view: S/U-mode reads are controlled by mcounteren.HPM10, and U-mode reads are additionally controlled by scounteren.HPM10. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter10 related to hpmcounter10?

mhpmcounter10 is the machine read/write counter; hpmcounter10 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM10, and U-mode reads are additionally controlled by scounteren.HPM10.