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CSR Bit Fields

RISC-V hpmcounter10 CSR Register

Address 0xC0APrivilege User (also accessible at higher privilege)Access RO / XLEN (upper 32 bits in hpmcounter10h on RV32)User counters and performance-monitoring CSRs

hpmcounter10 is a Zihpm unprivileged hardware performance-counter CSR. When implemented and accessible, it provides the count for a platform-selected performance event.

Related Search Terms
hpmcounter10 CSRhpmcounter10 0xC0AHPM counter 10mcounteren HPM10mhpmevent10
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand hpmcounter10 By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

The readable XLEN-bit view of the corresponding performance counter. On RV32 this CSR reads the low 32 bits and hpmcounter10h reads bits 63-32; the implemented counter count, width, and counted events are platform-specific.

VALUE (bits XLEN-1:0) — The readable XLEN-bit view of the corresponding performance counter. On RV32 this CSR reads the low 32 bits and hpmcounter10h reads bits 63-32; the implemented counter count, width, and counted events are platform-specific.

What This Field Controls

  • - The readable XLEN-bit view of the corresponding performance counter. On RV32 this CSR reads the low 32 bits and hpmcounter10h reads bits 63-32; the implemented counter count, width, and counted events are platform-specific.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hpmcounter10 is a read-only Zihpm user performance counter. Its event and implemented width are platform-specific, and user access can be limited by counter-enable CSRs.

hpmcounter10 is the standard user-level read-only CSR at 0xC0A.
Zihpm depends on Zicsr and provides up to 29 additional unprivileged 64-bit performance counters.
On RV32, hpmcounter10 reads the low 32 bits and hpmcounter10h reads the upper 32 bits.
An unimplemented counter may trap or return a constant; the counted event and counter count and width are platform-specific.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - Zihpm depends on Zicsr; hpmcounter10 is one of up to 29 unprivileged hardware performance counters.
  • - On privileged platforms, lower-privilege access can be controlled by counter-enable CSRs; disabled access causes an illegal-instruction exception.
  • - An unimplemented counter may raise an illegal-instruction exception or return a constant value; a misconfigured event selection may also make the counter return a constant value.

Risk Checks Before Writing

  • - hpmcounter10 is read-only; an attempt to write a read-only CSR raises an illegal-instruction exception.

Put It Back Into A Real Flow

1

Confirm Zihpm, counter implementation, and access permission.

2

Read hpmcounter10; on RV32 also read hpmcounter10h when a full 64-bit value is needed.

3

On privileged RISC-V platforms, interpret the result for the event selected by the corresponding mhpmevent10; other execution environments may provide alternative event-configuration mechanisms.

FAQ

Is hpmcounter10 always implemented and readable?

No. The implemented counter count is platform-specific; accessing an unimplemented counter may raise an illegal-instruction exception or return a constant. On privileged platforms, counter-enable CSRs can also prohibit lower-privilege access.

How are the upper 32 bits of hpmcounter10 read on RV32?

Use hpmcounter10h: hpmcounter10 reads the low 32 bits and hpmcounter10h reads bits 63-32 of the same counter.