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CSR Bit Fields

RISC-V mcounteren CSR Register

Address 0x306Privilege MachineAccess RW / 32Machine delegation, environment-configuration, and state-enable CSRs

Machine counter-enable register; controls whether lower privilege levels can access hardware counters.

Related Search Terms
mcounteren CSRmcounteren 0x306counter access enablemcounteren CY TM IRmcounteren HPMnS-mode counter access
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32HPM31:3RWIR2RWTM1RWCY0RW
Field Map

Understand mcounteren By Bit Fields

4 key fields
0

CY

RW

Enable cycle counter read in S/U mode

CY (bit 0) — Enable cycle counter read in S/U mode.

What This Field Controls

  • - Enable cycle counter read in S/U mode

Common Values

0Disabled

Lower-privilege reads of cycle are not authorized and raise an illegal-instruction exception.

1Enabled

Allows the next lower privilege level to read cycle; when S-mode exists, S-mode further gates U-mode access with scounteren.

1

TM

RW

Enable time counter read in S/U mode

TM (bit 1) — Enable time counter read in S/U mode.

What This Field Controls

  • - Enable time counter read in S/U mode

Common Values

0Disabled

Lower-privilege reads of time are not authorized and raise an illegal-instruction exception.

1Enabled

Allows the next lower privilege level to read time; when S-mode exists, S-mode further gates U-mode access with scounteren.

2

IR

RW

Enable instret counter read in S/U mode

IR (bit 2) — Enable instret counter read in S/U mode.

What This Field Controls

  • - Enable instret counter read in S/U mode

Common Values

0Disabled

Lower-privilege reads of instret are not authorized and raise an illegal-instruction exception.

1Enabled

Allows the next lower privilege level to read instret; when S-mode exists, S-mode further gates U-mode access with scounteren.

31:3

HPM

RW

Enable hpmcounter[3..31] read in S/U mode

HPM (bits 31:3) — Enable hpmcounter[3..31] read in S/U mode.

What This Field Controls

  • - Enable hpmcounter[3..31] read in S/U mode

Common Values

0Disabled

Lower-privilege reads of hpmcounter3-31 are not authorized and raise an illegal-instruction exception.

1Enabled

Allows the next lower privilege level to read hpmcounter3-31; when S-mode exists, S-mode further gates U-mode access with scounteren.

Official Basis & Search Notes

mcounteren is a RW CSR in machine delegation, environment-configuration, and state-enable csrs at 0x306. Check privilege and implemented extensions before interpreting its bit fields.

mcounteren address, lowest access privilege, and access class are checked against the official CSR table: 0x306, Machine, RW.
Read it as part of machine delegation, environment-configuration, and state-enable csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mcounteren; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x306 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mcounteren to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mcounteren be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcounteren as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcounteren?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.