Machine counter-enable register; controls availability of hardware performance-monitoring counters to the next-lower privileged mode.
Controls lower-privilege read access to cycle.
CY (bit 0) — Controls lower-privilege read access to cycle.
A less-privileged access to the corresponding CSR raises an illegal-instruction exception.
Permits access from the next implemented lower privilege mode; lower-level controls such as hcounteren, when present, must also allow it.
Controls lower-privilege read access to time; when clear, also blocks less-than-M access to stimecmp or vstimecmp.
TM (bit 1) — Controls lower-privilege read access to time; when clear, also blocks less-than-M access to stimecmp or vstimecmp.
A less-privileged access to the corresponding CSR raises an illegal-instruction exception.
Permits access from the next implemented lower privilege mode; lower-level controls such as hcounteren, when present, must also allow it.
Controls lower-privilege read access to instret.
IR (bit 2) — Controls lower-privilege read access to instret.
A less-privileged access to the corresponding CSR raises an illegal-instruction exception.
Permits access from the next implemented lower privilege mode; lower-level controls such as hcounteren, when present, must also allow it.
Controls lower-privilege read access to hpmcounter3 through hpmcounter31.
HPMn (bits 31:3) — Controls lower-privilege read access to hpmcounter3 through hpmcounter31.
A less-privileged access to the corresponding CSR raises an illegal-instruction exception.
Permits access from the next implemented lower privilege mode; lower-level controls such as hcounteren, when present, must also allow it.
mcounteren is a 32-bit register; in the RV64 CSR view, bits 63:32 contain no counter-enable bits and read as zero.
Reserved/RO0 (RV64) (bits 63:32) — mcounteren is a 32-bit register; in the RV64 CSR view, bits 63:32 contain no counter-enable bits and read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
mcounteren decides whether a lower privilege mode can read cycle, time, instret, and hpmcounter3-31. It does not affect whether the counters keep incrementing.
Decide which counters the next lower privilege mode may read.
Set only the corresponding WARL enable bits and read back to confirm the accepted value.
Use hcounteren/scounteren or state-enable controls as additional lower-level gates where applicable.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcounteren as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.