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CSR Bit Fields

RISC-V scounteren CSR Register

Address 0x106Privilege SupervisorAccess RW / 32Supervisor environment-configuration and state-enable CSRs

Supervisor counter-enable register controlling whether U-mode, and VU-mode when the H extension is implemented, may read standard counters and HPM counters.

Related Search Terms

scounteren CSR scounteren 0x106 U/VU-mode counter access scounteren CY TM IR scounteren HPMn hcounteren scounteren

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32RO0 HPMn31:3WARL/may be RO0 IR2WARL/may be RO0 TM1WARL/may be RO0 CY0WARL/may be RO0

Field Map

Understand scounteren By Bit Fields

5 key fields

CY

WARL/may be RO0

Controls U-mode reads of `cycle`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `cycle` traps; if this bit and `mcounteren.CY` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.CY` to be set.

CY (bit 0) — Controls U-mode reads of `cycle`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `cycle` traps; if this bit and `mcounteren.CY` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.CY` to be set.

What This Field Controls

- Controls U-mode reads of `cycle`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `cycle` traps; if this bit and `mcounteren.CY` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.CY` to be set.

Common Values

0Disabled

U-mode reads of cycle raise an illegal-instruction exception; when the H extension is implemented, VU-mode reads also trap because `scounteren.CY=0`.

1Enabled

S-mode authorizes U/VU-mode reads of cycle; U-mode still requires mcounteren.CY to be set, and VU-mode also requires hcounteren.CY to be set.

TM

WARL/may be RO0

Controls U-mode reads of `time`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `time` traps; if this bit and `mcounteren.TM` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.TM` to be set.

TM (bit 1) — Controls U-mode reads of `time`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `time` traps; if this bit and `mcounteren.TM` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.TM` to be set.

What This Field Controls

- Controls U-mode reads of `time`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `time` traps; if this bit and `mcounteren.TM` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.TM` to be set.

Common Values

0Disabled

U-mode reads of time raise an illegal-instruction exception; when the H extension is implemented, VU-mode reads also trap because `scounteren.TM=0`.

1Enabled

S-mode authorizes U/VU-mode reads of time; U-mode still requires mcounteren.TM to be set, and VU-mode also requires hcounteren.TM to be set.

IR

WARL/may be RO0

Controls U-mode reads of `instret`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `instret` traps; if this bit and `mcounteren.IR` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.IR` to be set.

IR (bit 2) — Controls U-mode reads of `instret`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `instret` traps; if this bit and `mcounteren.IR` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.IR` to be set.

What This Field Controls

- Controls U-mode reads of `instret`; when the H extension is implemented it also participates in VU-mode counter access checks. If clear, a U/VU-mode read of `instret` traps; if this bit and `mcounteren.IR` are both set, U-mode reads are permitted; VU-mode also requires `hcounteren.IR` to be set.

Common Values

0Disabled

U-mode reads of instret raise an illegal-instruction exception; when the H extension is implemented, VU-mode reads also trap because `scounteren.IR=0`.

1Enabled

S-mode authorizes U/VU-mode reads of instret; U-mode still requires mcounteren.IR to be set, and VU-mode also requires hcounteren.IR to be set.

31:3

HPMn

WARL/may be RO0

Each bit controls U-mode reads of the corresponding `hpmcounter3` through `hpmcounter31`; when the H extension is implemented it also participates in VU-mode counter access checks. Any bit may be read-only zero, indicating that a U/VU-mode read of the corresponding counter traps.

HPMn (bits 31:3) — Each bit controls U-mode reads of the corresponding `hpmcounter3` through `hpmcounter31`; when the H extension is implemented it also participates in VU-mode counter access checks. Any bit may be read-only zero, indicating that a U/VU-mode read of the corresponding counter traps.

What This Field Controls

- Each bit controls U-mode reads of the corresponding `hpmcounter3` through `hpmcounter31`; when the H extension is implemented it also participates in VU-mode counter access checks. Any bit may be read-only zero, indicating that a U/VU-mode read of the corresponding counter traps.

Common Values

0Disabled

U-mode reads of the corresponding hpmcounter raise an illegal-instruction exception; when the H extension is implemented, VU-mode reads also trap because the matching scounteren bit is 0.

1Enabled

S-mode authorizes U/VU-mode reads of the corresponding hpmcounter; U-mode still requires the matching mcounteren bit to be set, and VU-mode also requires the matching hcounteren bit to be set.

63:32

Reserved

RO0

`scounteren` is a 32-bit CSR; bits 63:32 in the RV64 view are reserved zero.

Reserved (bits 63:32) — `scounteren` is a 32-bit CSR; bits 63:32 in the RV64 view are reserved zero.

What This Field Controls

- `scounteren` is a 32-bit CSR; bits 63:32 in the RV64 view are reserved zero.

Common Values

0Reserved zero

These bits carry no counter-enable semantics.

Official Basis & Search Notes

scounteren controls U-mode reads of `cycle`, `time`, `instret`, and `hpmcounter3-31`; when the H extension is implemented it also participates in VU-mode counter access checks. Any bit may be read-only zero, U-mode still needs the matching `mcounteren` bit set, and VU-mode also needs the matching `hcounteren` bit.

The official Supervisor-Level ISA defines `scounteren` as a 32-bit register.

A clear CY/TM/IR/HPMn bit causes a U-mode read of the corresponding counter to raise an illegal-instruction exception; when the H extension is implemented it also blocks VU-mode reads.

The `mcounteren` setting does not affect whether a `scounteren` bit is writable, but U-mode access requires both corresponding bits to be set; VU-mode also requires the matching `hcounteren` bit to be set.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Supervisor-Level ISA RISC-V Privileged Architecture Manual: Hypervisor Counter-Enable

What To Check First When Reading This CSR

- `scounteren` is a mandatory 32-bit S-mode CSR, but any bit may be read-only zero.
- U-mode access to a counter requires the corresponding bits in both `scounteren` and `mcounteren` to be set; when the H extension is implemented, VU-mode also requires the matching `hcounteren` bit to be set.

Risk Checks Before Writing

- Do not assume all bits are writable; read back after writes according to WARL/read-only-zero behavior.
- Setting `scounteren` does not bypass `mcounteren` or `hcounteren` and does not decide whether a counter increments.

Put It Back Into A Real Flow

Confirm that M-mode has authorized the corresponding counter through `mcounteren`; for VU-mode, also confirm `hcounteren`.

S-mode sets the corresponding CY, TM, IR, or HPMn bit in `scounteren`.

Read the corresponding counter in U/VU-mode; an unauthorized read is expected to raise an illegal-instruction exception or an applicable virtual-instruction exception.

FAQ

Can scounteren be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records scounteren as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing scounteren?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.