RISC-V cycle CSR Register

Address 0xC00Privilege UserAccess RO / XLENUser counters and performance-monitoring CSRs

cycle is a user-level cycle counter CSR for the count visible through RDCYCLE.

Related Search Terms

cycle CSR cycle 0xC00 RDCYCLE CSR user cycle counter cycle counter read mcounteren CY

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RO

Field Map

Understand cycle By Bit Fields

1 key fields

XLEN-1:0

VALUE

Full register value of cycle; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

VALUE (bits XLEN-1:0) — Full register value of cycle; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

What This Field Controls

- Full register value of cycle; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

cycle is the user-level read-only cycle counter CSR at 0xC00, visible through RDCYCLE. Lower-privilege visibility can depend on counter-enable CSRs.

cycle address, lowest access privilege, and access class are checked against the official CSR table: 0xC00, User, RO.

cycle reads the cycle count; do not confuse it with time, instret, or hpmcounter event counts.

This is a read-only CSR; do not write it. Ignore reserved or WPRI field values on reads, and preserve those fields when writing other writable fields in the same CSR.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements cycle; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0xC00 and the lowest access privilege (User) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- cycle is a read-only CSR; writes raise an illegal-instruction exception or are disallowed by the implementation.

Put It Back Into A Real Flow

Read cycle to obtain hardware or runtime state.

Interpret the returned value according to the field descriptions and do not attempt to write it back.

If reading fails at the current privilege level, handle the illegal-instruction exception path.

FAQ

Can cycle be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records cycle as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using cycle?

cycle is read-only. Treat it as an observation point, do not try to write it, and do not depend on fixed values for reserved or WPRI fields.