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CSR Bit Fields

RISC-V cycle CSR Register

Address 0xC00Privilege UserAccess RO / XLEN bits (64-bit underlying counter)User counters and performance-monitoring CSRs

cycle is a Zicntr user-level read-only CSR that reads the low XLEN bits of clock cycles executed by the processor core from an arbitrary point in the past. Zicntr depends on Zicsr; the underlying counter is 64 bits, and RV32 uses cycleh to read bits 63:32.

Related Search Terms
cycle CSRcycle 0xC00RDCYCLE cycle counterRV32 cyclehmcounteren CY
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand cycle By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

Read-only low XLEN-bit view of cycle; the underlying counter is 64 bits. On RV32, cycleh reads bits 63:32.

VALUE (bits XLEN-1:0) — Read-only low XLEN-bit view of cycle; the underlying counter is 64 bits. On RV32, cycleh reads bits 63:32.

What This Field Controls

  • - Read-only low XLEN-bit view of cycle; the underlying counter is 64 bits. On RV32, cycleh reads bits 63:32.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

cycle is the Zicntr user-level read-only CSR at 0xC00, reading the low XLEN bits of a 64-bit underlying counter.

Zicntr depends on Zicsr; on RV32 the companion high-half CSR reads bits 63:32.
The cycle rate depends on the implementation and operating environment; the execution environment should provide a means to determine the current rate.
Read access in U-mode and virtualized execution is controlled by the CY bits in mcounteren, scounteren, and hcounteren.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - cycle is the low XLEN-bit view of a Zicntr read-only 64-bit counter; RV32 uses cycleh to read bits 63:32.
  • - The cycle rate depends on the implementation and operating environment; the execution environment should provide a means to determine the current rate.
  • - On privileged implementations with S-mode, U-mode reads require the CY bits in both mcounteren and scounteren; without S-mode, mcounteren controls U-mode access. When V=1, access is also subject to mcounteren and hcounteren; VU-mode also requires scounteren.

Risk Checks Before Writing

  • - cycle is read-only; writing a read-only CSR raises an illegal-instruction exception.

Put It Back Into A Real Flow

1

Read the low XLEN bits of cycle.

2

On RV32, use cycleh with it to read a 64-bit value.

3

Interpret the result using the execution environment counter definition, rate, and access controls.