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CSR Bit Fields

RISC-V hcounteren CSR Register

Address 0x606Privilege HypervisorAccess HRW / 32-bitHypervisor and virtualization CSRs

hcounteren is a Hypervisor counter-enable CSR.

Related Search Terms
hcounteren CSRhcounteren 0x606counter access enable bits for VS/VUcounter enable
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
RESERVED63:32RO0HPM31:3WARL (each bit may be RO0)IR2WARL (may be RO0)TM1WARL (may be RO0)CY0WARL (may be RO0)
Field Map

Understand hcounteren By Bit Fields

5 key fields
63:32

RESERVED

RO0

hcounteren is a 32-bit CSR; bits 63:32 in the RV64 view carry no hcounteren architectural state and read as zero.

RESERVED (bits 63:32) — hcounteren is a 32-bit CSR; bits 63:32 in the RV64 view carry no hcounteren architectural state and read as zero.

What This Field Controls

  • - hcounteren is a 32-bit CSR; bits 63:32 in the RV64 view carry no hcounteren architectural state and read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
0

CY

WARL (may be RO0)

Enables VS/VU access to cycle.

CY (bit 0) — Enables VS/VU access to cycle.

What This Field Controls

  • - Enables VS/VU access to cycle.

Common Values

0Disabled

VS/VU reads of cycle are not authorized by hcounteren; if the matching mcounteren bit is 1, access raises a virtual-instruction exception.

1Enabled

Allows cycle reads when V=1 unless another control prevents access.

↗Open Official Manual
1

TM

WARL (may be RO0)

Enables VS/VU access to time.

TM (bit 1) — Enables VS/VU access to time.

What This Field Controls

  • - Enables VS/VU access to time.

Common Values

0Disabled

VS/VU reads of time or VS access to vstimecmp are not authorized by hcounteren; if mcounteren.TM is 1, access raises a virtual-instruction exception.

1Enabled

Allows time reads when V=1 and, when Sstc is implemented, permits VS access to vstimecmp unless another control prevents access.

↗Open Official Manual
2

IR

WARL (may be RO0)

Enables VS/VU access to instret.

IR (bit 2) — Enables VS/VU access to instret.

What This Field Controls

  • - Enables VS/VU access to instret.

Common Values

0Disabled

VS/VU reads of instret are not authorized by hcounteren; if the matching mcounteren bit is 1, access raises a virtual-instruction exception.

1Enabled

Allows instret reads when V=1 unless another control prevents access.

↗Open Official Manual
31:3

HPM

WARL (each bit may be RO0)

Each HPMn bit controls permission to read the corresponding hpmcountern (n=3..31) when V=1.

HPM (bits 31:3) — Each HPMn bit controls permission to read the corresponding hpmcountern (n=3..31) when V=1.

What This Field Controls

  • - Each HPMn bit controls permission to read the corresponding hpmcountern (n=3..31) when V=1.

Common Values

0Disabled

A V=1 read of the corresponding hpmcountern raises a virtual-instruction exception when the matching mcounteren bit is 1; VU mode also requires the matching scounteren bit to be 1.

1Enabled

Allows reads of the corresponding hpmcounter3-31 when V=1 unless another control prevents access.

↗Open Official Manual
Official Basis & Search Notes

hcounteren is a Hypervisor counter-enable CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hcounteren address, access class, and width are checked against the official CSR tables: 0x606, HRW, and a 32-bit register.
hcounteren fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hcounteren is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - Every counter-permission bit may be read-only zero; setting hcounteren neither overrides mcounteren nor, in VU mode, removes the scounteren requirement.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hcounteren be accessed through a supervisor CSR alias?

Do not treat hcounteren as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.