RISC-V hedeleg CSR Register

Address 0x602Privilege HypervisorAccess HRW / HSXLEN / RV32 may use high-half CSRHypervisor and virtualization CSRs

hedeleg is a hypervisor exception delegation bitmap CSR.

Related Search Terms

hedeleg CSR hedeleg 0x602 hypervisor exception delegation VS delegation

Bit Overview

Hover for details · Click to jump↗Open Official Manual

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

EXCEPTION_DELEGATION63:0RW

Field Map

Understand hedeleg By Bit Fields

1 key fields

HSXLEN-1:0

EXCEPTION_DELEGATION

Each bit controls hypervisor delegation for the corresponding exception cause. The 0/1 delegation meaning applies only to writable, delegable synchronous exception cause bits.

EXCEPTION_DELEGATION (bits HSXLEN-1:0) — Each bit controls hypervisor delegation for the corresponding exception cause. The 0/1 delegation meaning applies only to writable, delegable synchronous exception cause bits.

What This Field Controls

- Each bit controls hypervisor delegation for the corresponding exception cause. The 0/1 delegation meaning applies only to writable, delegable synchronous exception cause bits.

Common Values

0Not delegated

Only for writable, delegable synchronous exception cause bits: 0 means not further delegated to VS-mode; unimplemented, non-delegable, or read-only-zero bits should not be interpreted with fixed delegation semantics.

1Delegated to VS-mode

Only for writable, delegable synchronous exception cause bits: 1 means further delegated to VS-mode when Hypervisor delegation conditions are met; unimplemented, non-delegable, or read-only-zero bits should not be interpreted with fixed delegation semantics.

↗Open Official Manual

Official Basis & Search Notes

hedeleg is a hypervisor exception delegation CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hedeleg address, access class, and width are checked against the official CSR tables: 0x602, HRW, HSXLEN / RV32 may use high-half CSR.

Each bit controls delegation for one exception cause; unimplemented or non-delegable bits follow official WARL/read-only-zero rules.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

- hedeleg is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hedeleg, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hedeleg be accessed through a supervisor CSR alias?

Do not treat hedeleg as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.