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CSR Bit Fields

RISC-V hedeleg CSR Register

Address 0x602Privilege HypervisorAccess HRW / 64-bit; RV32 accesses bits 63:32 through hedeleghHypervisor and virtualization CSRs

hedeleg is a 64-bit hypervisor synchronous-exception delegation CSR; synchronous traps already delegated to HS by medeleg can be further delegated to VS-mode when V=1 and the corresponding hedeleg bit is set.

Related Search Terms
hedeleg CSRhedeleg 0x602hedeleg Table 45hypervisor exception delegationhedelegh RV32
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Synchronous Exceptions63:0WARL
Field Map

Understand hedeleg By Bit Fields

1 key fields
63:0

Synchronous Exceptions

WARL

Each bit corresponds to the same-numbered synchronous exception cause; every bit must be writable or read-only zero, and Table 45 specifies several bits that must be writable or must be read-only zero.

Synchronous Exceptions (bits 63:0) — Each bit corresponds to the same-numbered synchronous exception cause; every bit must be writable or read-only zero, and Table 45 specifies several bits that must be writable or must be read-only zero.

What This Field Controls

  • - Each bit corresponds to the same-numbered synchronous exception cause; every bit must be writable or read-only zero, and Table 45 specifies several bits that must be writable or must be read-only zero.

Common Values

0Not further delegated

For writable delegable bits, 0 leaves the trap to be handled in HS-mode. Read-only-zero or non-delegable bits do not have settable delegation semantics.

1Further delegated to VS-mode

For writable delegable bits, 1 further delegates to VS-mode when the trap has been delegated to HS by medeleg and V=1 before the trap.

↗Open Official Manual
Official Basis & Search Notes

hedeleg controls further delegation of synchronous exceptions from HS to VS. It applies only to synchronous traps already delegated to HS by M-mode medeleg, and only when V=1 before the trap.

hedeleg address 0x602 and HRW access come from the Hypervisor CSR table; the register itself is 64 bits.
When XLEN=32, hedelegh is a 32-bit RW CSR aliasing hedeleg bits 63:32; when XLEN=64, hedelegh does not exist.
Each hedeleg bit must be writable or read-only zero; Table 45 enumerates exception-cause bits that must be writable or must be read-only zero.
Only synchronous traps already delegated to HS by medeleg, with V=1 before the trap and the matching hedeleg bit set, are further delegated to VS-mode.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hedeleg is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hedeleg, rely only on writable delegable exception-cause bits; read-only-zero bits cannot be set to delegate.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H extension is implemented and that the corresponding synchronous trap has first been delegated to HS by medeleg.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hedeleg be accessed through a supervisor CSR alias?

No. hedeleg is an H-level CSR, not a VS CSR copy; direct VS/VU access to an implemented hypervisor CSR raises a virtual-instruction exception under the H-extension rules.