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CSR Bit Fields

RISC-V hideleg CSR Register

Address 0x603Privilege HypervisorAccess HRW / HSXLEN / RV32 may use high-half CSRHypervisor and virtualization CSRs

hideleg is a hypervisor interrupt delegation bitmap CSR.

Related Search Terms
hideleg CSRhideleg 0x603hypervisor interrupt delegationVS delegation
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
PLATFORM_INTERRUPT_DELEGATION63:16WARLRESERVED0RO0
Field Map

Understand hideleg By Bit Fields

5 key fields
HSXLEN-1:16

PLATFORM_INTERRUPT_DELEGATION

WARL

Delegation bits for platform interrupt causes; only implemented causes already delegated to HS by mideleg can be further delegated to VS.

PLATFORM_INTERRUPT_DELEGATION (bits HSXLEN-1:16) — Delegation bits for platform interrupt causes; only implemented causes already delegated to HS by mideleg can be further delegated to VS.

What This Field Controls

  • - Delegation bits for platform interrupt causes; only implemented causes already delegated to HS by mideleg can be further delegated to VS.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:14, 11, 8:7, 4:3, 0

RESERVED

RO0

Standard reserved bits; read as zero.

RESERVED (bits 15:14, 11, 8:7, 4:3, 0) — Standard reserved bits; read as zero.

What This Field Controls

  • - Standard reserved bits; read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
13

LCOFI_DELEGATION

WARL / RO0 without Shlcofideleg

Delegates the local counter-overflow interrupt when Shlcofideleg is implemented; otherwise reads zero.

LCOFI_DELEGATION (bit 13) — Delegates the local counter-overflow interrupt when Shlcofideleg is implemented; otherwise reads zero.

What This Field Controls

  • - Delegates the local counter-overflow interrupt when Shlcofideleg is implemented; otherwise reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12, 9, 5, 1

S_LEVEL_INTERRUPT_DELEGATION

RO0

The standard S-level guest-external, external, timer, and software interrupt positions are read-only zero.

S_LEVEL_INTERRUPT_DELEGATION (bits 12, 9, 5, 1) — The standard S-level guest-external, external, timer, and software interrupt positions are read-only zero.

What This Field Controls

  • - The standard S-level guest-external, external, timer, and software interrupt positions are read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
10, 6, 2

VS_LEVEL_INTERRUPT_DELEGATION

RW

Delegates VS external, timer, and software interrupts respectively; the corresponding cause must already be delegated to HS by mideleg.

VS_LEVEL_INTERRUPT_DELEGATION (bits 10, 6, 2) — Delegates VS external, timer, and software interrupts respectively; the corresponding cause must already be delegated to HS by mideleg.

What This Field Controls

  • - Delegates VS external, timer, and software interrupts respectively; the corresponding cause must already be delegated to HS by mideleg.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hideleg is a hypervisor interrupt delegation CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hideleg address, access class, and width are checked against the official CSR tables: 0x603, HRW, HSXLEN / RV32 may use high-half CSR.
Each bit controls delegation for one interrupt cause; unimplemented or non-delegable bits follow official WARL/read-only-zero rules.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hideleg is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - Before writing hideleg, confirm that mideleg delegates the cause to HS; do not write standard read-only-zero positions, and handle platform causes only as implementation documents specify.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hideleg be accessed through a supervisor CSR alias?

Do not treat hideleg as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.