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CSR Bit Fields

RISC-V hie CSR Register

Address 0x604Privilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hie is a Hypervisor interrupt-enable CSR.

Related Search Terms
hie CSRhie 0x604hypervisor interrupt-enable bitsHypervisor
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
PLATFORM_INTERRUPT_ENABLE63:16WARLRESERVED1:0RO0
Field Map

Understand hie By Bit Fields

6 key fields
HSXLEN-1:16

PLATFORM_INTERRUPT_ENABLE

WARL

Enable bits for platform interrupts; an implemented bit is writable only if its interrupt can become pending in hip, otherwise it reads zero.

PLATFORM_INTERRUPT_ENABLE (bits HSXLEN-1:16) — Enable bits for platform interrupts; an implemented bit is writable only if its interrupt can become pending in hip, otherwise it reads zero.

What This Field Controls

  • - Enable bits for platform interrupts; an implemented bit is writable only if its interrupt can become pending in hip, otherwise it reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:13, 11, 9, 8:7, 5, 4:3, 1:0

RESERVED

RO0

Standard reserved bits; read as zero.

RESERVED (bits 15:13, 11, 9, 8:7, 5, 4:3, 1:0) — Standard reserved bits; read as zero.

What This Field Controls

  • - Standard reserved bits; read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12

SGEIE

RW / RO0 without guest external interrupts

Enables the HS-level guest external interrupt; hip.SGEIP is set when hgeip AND hgeie has any nonzero bit.

SGEIE (bit 12) — Enables the HS-level guest external interrupt; hip.SGEIP is set when hgeip AND hgeie has any nonzero bit.

What This Field Controls

  • - Enables the HS-level guest external interrupt; hip.SGEIP is set when hgeip AND hgeie has any nonzero bit.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
10

VSEIE

RW

Enables the VS-level external interrupt; the corresponding hip.VSEIP is read-only pending state.

VSEIE (bit 10) — Enables the VS-level external interrupt; the corresponding hip.VSEIP is read-only pending state.

What This Field Controls

  • - Enables the VS-level external interrupt; the corresponding hip.VSEIP is read-only pending state.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
6

VSTIE

RW

Enables the VS-level timer interrupt; with Sstc, the vstimecmp timer signal can also set hip.VSTIP.

VSTIE (bit 6) — Enables the VS-level timer interrupt; with Sstc, the vstimecmp timer signal can also set hip.VSTIP.

What This Field Controls

  • - Enables the VS-level timer interrupt; with Sstc, the vstimecmp timer signal can also set hip.VSTIP.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
2

VSSIE

RW

Enables the VS-level software interrupt; hip.VSSIP is a writable alias of the same hvip bit.

VSSIE (bit 2) — Enables the VS-level software interrupt; hip.VSSIP is a writable alias of the same hvip bit.

What This Field Controls

  • - Enables the VS-level software interrupt; hip.VSSIP is a writable alias of the same hvip bit.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hie is a Hypervisor interrupt-enable CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hie address, access class, and width are checked against the official CSR tables: 0x604, HRW, HSXLEN.
hie fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hie is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - Enable only interrupts that can become pending in hip; a corresponding writable sie bit is read-only zero in hie.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hie be accessed through a supervisor CSR alias?

Do not treat hie as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.