RISC-V cycleh CSR Register

Address 0xC80Privilege UserAccess RO / RV32 high-half / 32-bitUser counters and performance-monitoring CSRs

cycleh is the RV32 high-half CSR for the user cycle counter.

Related Search Terms

cycleh CSR cycleh 0xC80 RV32 cycle high RDCYCLE high half 64-bit cycle read user cycleh CSR

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32VALUE31:0RO

Field Map

Understand cycleh By Bit Fields

1 key fields

31:0

VALUE

Full register value of cycleh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

VALUE (bits 31:0) — Full register value of cycleh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

What This Field Controls

- Full register value of cycleh; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

cycleh is the RV32 user-level read-only high-half counter CSR at 0xC80, used with cycle for wider cycle-count reads.

cycleh address, lowest access privilege, and access class are checked against the official CSR table: 0xC80, User, RO.

cycleh is for reading the high half of cycle on RV32; RV64 does not need this high-half CSR.

This is a read-only CSR; do not write it. Ignore reserved or WPRI field values on reads, and preserve those fields when writing other writable fields in the same CSR.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements cycleh; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0xC80 and the lowest access privilege (User) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- cycleh is a read-only CSR; writes raise an illegal-instruction exception or are disallowed by the implementation.

Put It Back Into A Real Flow

Read cycleh to obtain hardware or runtime state.

Interpret the returned value according to the field descriptions and do not attempt to write it back.

If reading fails at the current privilege level, handle the illegal-instruction exception path.

FAQ

Can cycleh be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records cycleh as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using cycleh?

cycleh is read-only. Treat it as an observation point, do not try to write it, and do not depend on fixed values for reserved or WPRI fields.