RISC-V instret CSR Register

Address 0xC02Privilege UserAccess RO / XLENUser counters and performance-monitoring CSRs

instret is a user-level instructions-retired counter CSR for the count visible through RDINSTRET.

Related Search Terms

instret CSR instret 0xC02 RDINSTRET CSR user instret counter retired instruction count mcounteren IR

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RO

Field Map

Understand instret By Bit Fields

1 key fields

XLEN-1:0

VALUE

instret is a read-only shadow of `minstret`: RV64 reads the complete 64-bit counter and RV32 reads bits 31:0. Defined by Zicntr, it counts instructions retired by this hart since an arbitrary point in the past. Synchronous exceptions, including ECALL and EBREAK, do not retire and therefore do not increment it.

VALUE (bits XLEN-1:0) — instret is a read-only shadow of `minstret`: RV64 reads the complete 64-bit counter and RV32 reads bits 31:0. Defined by Zicntr, it counts instructions retired by this hart since an arbitrary point in the past. Synchronous exceptions, including ECALL and EBREAK, do not retire and therefore do not increment it.

What This Field Controls

- instret is a read-only shadow of `minstret`: RV64 reads the complete 64-bit counter and RV32 reads bits 31:0. Defined by Zicntr, it counts instructions retired by this hart since an arbitrary point in the past. Synchronous exceptions, including ECALL and EBREAK, do not retire and therefore do not increment it.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

instret is the user-level read-only retired-instruction counter CSR at 0xC02, visible through RDINSTRET. Lower-privilege visibility can depend on counter-enable CSRs.

instret address, lowest access privilege, and access class are checked against the official CSR table: 0xC02, User, RO.

instret reads retired-instruction counts; do not confuse it with cycle counts, timer values, or hpmcounter event counts.

This is a read-only CSR; do not write it. Ignore reserved or WPRI field values on reads, and preserve those fields when writing other writable fields in the same CSR.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements instret; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0xC02 and the lowest access privilege (User) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- instret is a read-only CSR; an attempted write raises an illegal-instruction exception.

Put It Back Into A Real Flow

Read instret to obtain hardware or runtime state.

Interpret the returned value according to the field descriptions and do not attempt to write it back.

If a read is blocked, handle the applicable illegal-instruction or virtual-instruction exception path.

FAQ

Can instret be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records instret as User. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when using instret?

instret is read-only. Treat it as an observation point, do not try to write it, and do not depend on fixed values for reserved or WPRI fields.